HDMI Intel® Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 1/26/2024
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.7. HDMI Intel® FPGA IP Design Example Parameters

Table 5.   HDMI Intel® FPGA IP Design Example Parameters for Intel® Cyclone® 10 GX DevicesThese options are available for Intel® Cyclone® 10 GX devices only.

Parameter

Value

Description

Available Design Example
Select Design

Cyclone 10 HDMI RX-TX Retransmit

Select the design example to be generated. The generated design example has pre-configured parameter settings. It does not follow user settings.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Synthesis On, Off Turn on this option to generate the necessary files for Intel® Quartus® Prime compilation and hardware demonstration.

Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.

Target Development Kit

Select Board

No Development Kit,

Cyclone 10 GX FPGA Development Kit,

Custom Development Kit

 Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Cyclone 10 GX FPGA Development Kit : This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
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