HDMI Intel® Cyclone® 10 GX FGPA IP Design Example User Guide

Download PDF
ID 683309
Date 1/26/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

2.7. Hardware Setup

The HDMI Intel® FPGA IP design example is HDMI 2.0 capable and performs a loop-through demonstration for a standard HDMI video stream.
To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the Transceiver Native PHY RX block, and the HDMI sink input.
  1. The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
  2. The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX core through the DCFIFO.
  3. The HDMI source port of the FMC daughter card transmits the image to a monitor.
Note: If you use another Intel FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Intel® Cyclone® 10 GX FPGA development kit and Bitec HDMI 2.0 daughter card. You may modify the settings for your own board.
On-board Push Button, DIP Switch, and User LED Functions
LEDs Function
user_dipsw[0]
  • Set 0 (in the design example) and push the board switch to ON = HDMI TX core to send the DVI encoded signal
  • Set 1 (in the design example) and push the board switch to OFF = HDMI TX core to send the HDMI encoded signal
user_pb[0] Press once to perform system reset.
user_pb[1] Press once to toggle the HPD signal to the standard HDMI source.
user_pb[2]
  • Press and hold to instruct the TX core to stop sending the InfoFrames from the sideband signals.
  • Release to resume sending the InfoFrames from the sideband signals.
USER_LED[0]
RX HDMI PLL lock status or RX transceiver ready status.
  • 0 = RX HDMI PLL unlocked or RX transceiver is not ready
  • 1 = RX HDMI PLL locked or RX transceiver is ready
USER_LED[1]
RX HDMI core lock status.
  • 0 = At least 1 channel unlocked
  • 1 = All 3 channels locked
USER_LED[2]
TX HDMI PLL lock status, TX transceiver PLL lock status, or TX transceiver ready status.
  • 0 = TX HDMI PLL unlocked, TX transceiver PLL unlocked, or TX transceiver is not ready
  • 1 = TX HDMI PLL locked, TX transceiver PLL locked, or TX transceiver is ready
USER_LED[3]
TX or RX oversampling status.
  • 0 = Non-oversampled (data rate > 1,000 Mbps in Intel® Cyclone® 10 GX device)
  • 1 = Oversampled (data rate < 1,000 Mbps in Intel® Cyclone® 10 GX device)
Level Two Title