2.8. Simulation Testbench
The simulation testbench simulates the HDMI TX serial loopback to the RX core.
Note: This simulation testbench is not supported for designs with the Include I2C parameter enabled.
Figure 10. HDMI Intel® FPGA IP Simulation Testbench Block Diagram
Component | Description |
---|---|
Video TPG | The video test pattern generator (TPG) provides the video stimulus. |
Audio Sample Gen | The audio sample generator provides audio sample stimulus. The generator generates an incrementing test data pattern to be transmitted through the audio channel. |
Aux Sample Gen | The aux sample generator provides the auxiliary sample stimulus. The generator generates a fixed data to be transmitted from the transmitter. |
CRC Check | This checker verifies if the TX transceiver recovered clock frequency matches the desired data rate. |
Audio Data Check | The audio data check compares whether the incrementing test data pattern is received and decoded correctly. |
Aux Data Check | The aux data check compares whether the expected aux data is received and decoded correctly on the receiver side. |
The HDMI simulation testbench does the following verification tests:
HDMI Feature | Verification |
---|---|
Video data |
|
Auxiliary data |
|
Audio data |
|
A successful simulation ends with the following message:
# SYMBOLS_PER_CLOCK = 2 # VIC = 4 # FRL_RATE = 0 # BPP = 0 # AUDIO_FREQUENCY (kHz) = 48 # AUDIO_CHANNEL = 8 # Simulation pass
Simulator | Verilog HDL | VHDL |
---|---|---|
ModelSim* - Intel® FPGA Edition/ ModelSim* - Intel® FPGA Starter Edition | Yes | Yes |
VCS* / VCS* MX | Yes | Yes |
Riviera-PRO* | Yes | Yes |
Xcelium* Parallel | Yes | No |