AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software

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ID 683299
Date 2/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software x
1.1. Features 1.2. Overview 1.3. Programming Single and Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core 1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software 1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software 1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer 1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.8. Intel® FPGA Serial Flash Loader IP Core Parameter 1.9. Intel® FPGA Serial Flash Loader IP Core Signals 1.10. Document Revision History for AN 370: Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software x
1.4.1. Instantiating the Intel® FPGA Serial Flash Loader IP Core
1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software x
1.5.1. Converting .sof to .jic Files in the Intel® Quartus® Prime Software 1.5.2. Converting .jic Files to .jam Files in the Intel® Quartus® Prime Software
1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer x
1.6.1. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jic Files 1.6.2. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jam Files
1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.7.1. Multiple Configuration Devices Support 1.7.2. Boot Page Selection
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software

1.9. Intel® FPGA Serial Flash Loader IP Core Signals

Table 4.   Intel® FPGA Serial Flash Loader IP Core Signals
Signal Direction Width (Bits) Description
dclk_in 1 Input 1 Clock signal from your FPGA design to the external DCLK pin through the ASMI hard logic.

The clock frequency of the dclk_in signal depends on your design and the flash frequency.

Both inputs and output must be synchronous to dclk_in.

ncso_in 1 Input 1 Control signal from your FPGA design to the nCSO pin. A low signal enables the serial configuration device.
Note: This signal is 3 bits width for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
asdo_in 2 Input 1 Control signal from your FPGA design to the ASDO pin for sending data into the serial configuration device.
noe_in Input 1 Control signal to enable the Intel® FPGA Serial Flash Loader IP core. A low signal enables the IP core. The IP core tri-states the ASMI interface when the IP core is disabled.

If you do not access ASMI interface externally, for example, from a microprocessor, leave this signal tied to GND.

This signal is available for all device families.

asmi_access_granted 1 Input 1 Control signal to allow the Intel® FPGA Serial Flash Loader IP core to access the following pins using the ASMI interface:
  • dclk_in
  • ncso_in
  • asdo_in
  • data0_out
  • data_in
  • data_oe
  • data_out
A high signal allows the Intel® Serial Flash Loader IP core to access the ASMI interface. A low signal allows your FPGA design to access the ASMI interface.

Always keep this signal low. The user logic must always monitor the asmi_access_request signal. If the asmi_access_request signal is asserted, the user logic may assert the asmi_access_granted signal to allow the JTAG interface to access the Intel® FPGA Serial Flash Loader IP core.

The user logic must continue to drive the asmi_access_granted signal until the Intel® FPGA Serial Flash Loader IP core deasserts the asmi_access_request signal.

This signal is not synchronous with the dclk_in signal.

Note: The user interface is the master and the JTAG interface is the slave.
data0_out 2 Output 1 Signal from the DATA0 pin to your FPGA design.
asmi_access_request 1 Output 1 A high signal indicates that the Intel® FPGA Serial Flash Loader IP core is requesting ASMI interface access. The Intel® FPGA Serial Flash Loader IP core starts accessing the ASMI interface when the ASMI_ACCESS_GRANTED is high. The asmi_access_request signal stays high until the Intel® FPGA Serial Flash Loader IP core operation ends, such as Program/Configure, Verify, Blank Check, Examine, Erase and Auto-detect. If the asmi_access_granted signal is not asserted five seconds after the asmi_access_request signal goes high, the Intel® FPGA Serial Flash Loader IP core operation fails.

This signal is not synchronous with the dclk_in signal.

data_in[] 3 Input 4 Control signal from your FPGA design to the AS data pin for sending data into the serial configuration device.
data_out[] 3 Output 4 Signal from the AS data pin to your FPGA design.
data_oe[] 3 Input 4 Controls data pin either as input or output because the dedicated pins for active serial data is bidirectional.

To set the AS data pin as input, set the desired data pin oe to 0.

To set the AS data pin as output, set the desired data pin oe to 1.

1 Available for all device families when you turn on the Share ASMI interface with your design parameter.
2 Available for Arria® II, Intel® Cyclone® 10 LP, Cyclone® IV, and Stratix® IV device families when you turn on the Share ASMI interface with your design parameter.
3 Available for Arria® V, Arria® V GZ, Intel® Arria® 10, Intel® Cyclone® 10 GX, Cyclone V, and Stratix V devices only when you turn on the Share ASMI interface with your design parameter.
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