Mailbox Client Intel® FPGA IPs User Guide

ID 683290
Date 4/01/2024
Public

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1.4. Mailbox Client Intel® FPGA IP Core Interface Signals

The host communicates with the Mailbox Client Intel® FPGA IP over its Avalon® memory-mapped interface.

Through the AXI manager interface, the crypto service has access to the lowest 1GB of memory, with a maximum data size of 512 MB per each read and write operation.

Note: For Agilex™ 7 and Agilex™ 5 devices, the AXI manager interface is available if you enabled the Enable Crypto Service parameter.
The following figure illustrates the Mailbox Client Intel® FPGA IP interfaces.
Figure 2.  Mailbox Client Intel® FPGA IP InterfacesThe AXI manager interface is only available in the Agilex™ 7 and Agilex™ 5 devices with the Enable Crypto Service parameter enabled.
Note: For information about the AXI manager interface, refer to the AXI Manager Interface table.
Note: The avmm_waitrequest signal is mandatory in Quartus® Prime software version 23.2 or later.