IOPLL Intel® FPGA IP Core User Guide

Download PDF
ID 683285
Date 2/06/2023
Public
Document Table of Contents
Document Table of Contents x
IOPLL Intel® FPGA IP Core User Guide
IOPLL Intel® FPGA IP Core User Guide x
Device Family Support IOPLL IP Core Parameters Functional Description IOPLL Intel® FPGA IP Core User Guide Archives Document Revision History for the IOPLL Intel® FPGA IP Core User Guide
IOPLL IP Core Parameters x
IOPLL IP Core Parameters - PLL Tab IOPLL IP Core Parameters - Settings Tab IOPLL IP Core Parameters - Cascading Tab IOPLL IP Core Parameters - Dynamic Reconfiguration Tab IOPLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading Ports
IOPLL Intel® FPGA IP Core User Guide

Reference Clock Switchover

The reference clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy, or for a dual clock domain application such as in a system. The system can turn on a redundant clock if the primary clock stops running.

Using the reference clock switchover feature, you can specify the frequency for the second input clock, and select the mode and delay for the switchover.

The clock loss detection and reference clock switchover block has the following functions:

  • Monitors the reference clock status. If the reference clock fails, the clock automatically switches to a backup clock input source. The clock updates the status of the clkbad and activeclk signals to alert the event.
  • Switches the reference clock back and forth between two different frequencies. Use the extswitch signal to manually control the switch action. After a switchover occurs, the PLL may lose lock temporarily and go through the reckoning process.
Level Two Title