IOPLL Intel® FPGA IP Core User Guide

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ID 683285
Date 2/06/2023
Public
Document Table of Contents
Document Table of Contents x
IOPLL Intel® FPGA IP Core User Guide
IOPLL Intel® FPGA IP Core User Guide x
Device Family Support IOPLL IP Core Parameters Functional Description IOPLL Intel® FPGA IP Core User Guide Archives Document Revision History for the IOPLL Intel® FPGA IP Core User Guide
IOPLL IP Core Parameters x
IOPLL IP Core Parameters - PLL Tab IOPLL IP Core Parameters - Settings Tab IOPLL IP Core Parameters - Cascading Tab IOPLL IP Core Parameters - Dynamic Reconfiguration Tab IOPLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading Ports
IOPLL Intel® FPGA IP Core User Guide

Building Blocks of a PLL

The main blocks of the I/O PLL are the phase frequency detector (PFD), charge pump, loop filter, VCO, and counters, such as a feedback counter (M), a pre-scale counter (N), and post-scale counters (C). The PLL architecture depends on the device you use in your design.

Figure 1. Typical I/O PLL Architecture

The following terms are commonly used to describe the behavior of a PLL:

  • PLL lock time—also known as the PLL acquisition time. PLL lock time is the time for the PLL to attain the target frequency and phase relationship after power-up, after a programmed output frequency change, or after a PLL reset.
    Note: Simulation software does not model a realistic PLL lock time. Simulation shows an unrealistically fast lock time. For the actual lock time specification, refer to the device datasheet.
  • PLL resolution—the minimum frequency increment value of a PLL VCO. The number of bits in the M and N counters determine the PLL resolution value.
  • PLL sample rate—the FREF sampling frequency required to perform the phase and frequency correction in the PLL. The PLL sample rate is fREF /N.
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