IOPLL Intel® FPGA IP Core User Guide

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ID 683285
Date 2/06/2023
Public
Document Table of Contents
Document Table of Contents x
IOPLL Intel® FPGA IP Core User Guide
IOPLL Intel® FPGA IP Core User Guide x
Device Family Support IOPLL IP Core Parameters Functional Description IOPLL Intel® FPGA IP Core User Guide Archives Document Revision History for the IOPLL Intel® FPGA IP Core User Guide
IOPLL IP Core Parameters x
IOPLL IP Core Parameters - PLL Tab IOPLL IP Core Parameters - Settings Tab IOPLL IP Core Parameters - Cascading Tab IOPLL IP Core Parameters - Dynamic Reconfiguration Tab IOPLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading Ports
IOPLL Intel® FPGA IP Core User Guide

Output Clocks

The IOPLL IP core can generate up to nine clock output signals. The generated clock output signals clock the core or the external blocks outside the core.

You can use the reset signal to reset the output clock value to 0 and disable the PLL output clocks.

Each output clock has a set of requested settings where you can specify the desired values for output frequency, phase shift, and duty cycle. The desired settings are the settings that you want to implement in your design.

The actual values for the frequency, phase shift, and duty cycle are the closest settings (best approximate of the desired settings) that can be implemented in the PLL circuit.

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