IOPLL Intel® FPGA IP Core User Guide

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ID 683285
Date 2/06/2023
Public
Document Table of Contents
Document Table of Contents x
IOPLL Intel® FPGA IP Core User Guide
IOPLL Intel® FPGA IP Core User Guide x
Device Family Support IOPLL IP Core Parameters Functional Description IOPLL Intel® FPGA IP Core User Guide Archives Document Revision History for the IOPLL Intel® FPGA IP Core User Guide
IOPLL IP Core Parameters x
IOPLL IP Core Parameters - PLL Tab IOPLL IP Core Parameters - Settings Tab IOPLL IP Core Parameters - Cascading Tab IOPLL IP Core Parameters - Dynamic Reconfiguration Tab IOPLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading Ports
IOPLL Intel® FPGA IP Core User Guide

IOPLL IP Core Parameters - Settings Tab

Table 2.   IOPLL IP Core Parameters - Settings Tab
Parameter Legal Value Description
PLL Bandwidth Preset Low, Medium, or High Specifies the PLL bandwidth preset setting. The default selection is Low.
PLL Auto Reset Turn on or Turn off Automatically self-resets the PLL on loss of lock.
Create a second input clk ‘refclk1’ Turn on or Turn off Turn on to provide a backup clock attached to your PLL that can switch with your original reference clock.
Second Reference Clock Frequency — Selects the frequency of the second input clock signal. The default value is 100.0 MHz. The minimum and maximum value is dependent on the device used.
Create an ‘active_clk’ signal to indicate the input clock in use Turn on or Turn off Turn on to create the activeclk output. The activeclk output indicates the input clock which is in use by the PLL. Output signal low indicates refclk and output signal high indicates refclk1.
Create a ‘clkbad’ signal for each of the input clocks Turn on or Turn off Turn on to create two clkbad outputs, one for each input clock. Output signal low indicates the clock is working and output signal high indicates the clock is not working.
Switchover Mode Automatic Switchover, Manual Switchover, or Automatic Switchover with Manual Override Specifies the switchover mode for design application. The IP supports three switchover modes:
  • If you select the Automatic Switchover mode, the PLL circuitry monitors the selected reference clock. If one clock stops, the circuit automatically switches to the backup clock in a few clock cycles and updates the status signals, clkbad and activeclk.
  • If you select the Manual Switchover mode, when the control signal, extswitch, changes from logic high to logic low, and stays low for at least three clock cycles, the input clock switches to the other clock. The extswitch can be generated from FPGA core logic or input pin.
  • If you select Automatic Switchover with Manual Override mode, when the extswitch signal is low, it overrides the automatic switch function. As long as extswitch remains low, further switchover action is blocked. To select this mode, your two clock sources must be running and the frequency of the two clocks cannot differ by more than 20%. If both clocks are not on the same frequency, but their period difference is within 20%, the clock loss detection block can detect the lost clock. The PLL most likely drops out of lock after the PLL clock input switchover and needs time to lock again.
Switchover Delay 0–7 Adds a specific amount of cycle delay to the switchover process. The default value is 0.
Access to PLL LVDS_CLK/LOADEN output port Disabled, Enable LVDS_CLK/LOADEN 0, or Enable LVDS_CLK/LOADEN 0 & 1

Select Enable LVDS_CLK/LOADEN 0 or Enable LVDS_CLK/LOADEN 0 & 1 to enable the PLL lvds_clk or loaden output port.

Enables this parameter in case the PLL feeds an LVDS SERDES block with external PLL.

When using the I/O PLL outclk ports with LVDS ports, outclk[0..3] are used for lvds_clk[0,1] and loaden[0,1] ports, outclk4 can be used for coreclk ports.

Enable access to the PLL DPA output port Turn on or Turn off Turn on to enable the PLL DPA output port.
Enable access to PLL external clock output port Turn on or Turn off Turn on to enable the PLL external clock output port.
Specifies which outclk to be used as extclk_out[0] source C0 – C8 Specifies the outclk port to be used as extclk_out[0] source.
Specifies which outclk to be used as extclk_out[1] source C0 – C8 Specifies the outclk port to be used as extclk_out[1] source.
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