IOPLL Intel® FPGA IP Core User Guide

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ID 683285
Date 2/06/2023
Public
Document Table of Contents
Document Table of Contents x
IOPLL Intel® FPGA IP Core User Guide
IOPLL Intel® FPGA IP Core User Guide x
Device Family Support IOPLL IP Core Parameters Functional Description IOPLL Intel® FPGA IP Core User Guide Archives Document Revision History for the IOPLL Intel® FPGA IP Core User Guide
IOPLL IP Core Parameters x
IOPLL IP Core Parameters - PLL Tab IOPLL IP Core Parameters - Settings Tab IOPLL IP Core Parameters - Cascading Tab IOPLL IP Core Parameters - Dynamic Reconfiguration Tab IOPLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading Ports
IOPLL Intel® FPGA IP Core User Guide

IOPLL Intel® FPGA IP Core User Guide Archives

For the latest and previous versions of this user guide, refer to IOPLL Intel FPGA IP Core User Guide. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

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