IOPLL Intel® FPGA IP Core User Guide

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ID 683285
Date 2/06/2023
Public
Document Table of Contents
Document Table of Contents x
IOPLL Intel® FPGA IP Core User Guide
IOPLL Intel® FPGA IP Core User Guide x
Device Family Support IOPLL IP Core Parameters Functional Description IOPLL Intel® FPGA IP Core User Guide Archives Document Revision History for the IOPLL Intel® FPGA IP Core User Guide
IOPLL IP Core Parameters x
IOPLL IP Core Parameters - PLL Tab IOPLL IP Core Parameters - Settings Tab IOPLL IP Core Parameters - Cascading Tab IOPLL IP Core Parameters - Dynamic Reconfiguration Tab IOPLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading Ports
IOPLL Intel® FPGA IP Core User Guide

Document Revision History for the IOPLL Intel® FPGA IP Core User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.02.06 18.1 Added a footnote in the PLL Lock topic.
2019.06.24 18.1 Updated the description for dedicated clock inputs in the Typical I/O PLL Architecture diagram.
2019.01.03 18.1
  • Updated the Access to PLL LVDS_CLK/LOADEN output port parameter in the IOPLL IP Core Parameters - Settings Tab table.
  • Updated the description for the zdbfbclk port in the IOPLL IP Core Ports table.
2018.09.28 18.1
  • Corrected the description for extswitch in the IOPLL IP Core Ports table.
  • Renamed the following IP cores as per Intel rebranding:
    • Changed Altera IOPLL IP core to IOPLL Intel FPGA IP core.
    • Changed Altera PLL Reconfig IP core to PLL Reconfig Intel FPGA IP core.
    • Changed Arria 10 FPLL IP core to fPLL Intel Arria 10/Cyclone 10 FPGA IP core.
Date Version Changes
June 2017 2017.06.16
  • Added support for Intel® Cyclone® 10 GX devices.
  • Rebranded as Intel.
December 2016 2016.12.05 Updated the description of the rst port of the Altera PLL IP core.
June 2016 2016.06.23
  • Updated Altera PLL IP Core Parameters - Settings Tab table.
    • Updated the description for Manual Switchover and Automatic Switchover with Manual Override parameters. The clock switchover control signal is active low.
    • Updated the description for Switchover Delay parameter.
  • Defined M and C counters for DPS Counter Selection parameter in Altera PLL IP Core Parameters - Dynamic Reconfiguration Tab table.
  • Changed clock switchover port name from clkswitch to extswitch in Typical I/O PLL Architecture diagram.
May 2016 2016.05.02 Updated Altera PLL IP Core Parameters - Dynamic Reconfiguration Tab table.
May 2015 2015.05.04 Updated the description for Enable access to PLL LVDS_CLK/LOADEN output port parameter in Altera PLL IP Core Parameters - Settings Tab table. Added a link to the Signal Interface Between Altera IOPLL and Altera LVDS SERDES IP Cores table in the I/O and High Speed I/O in Arria 10 Devices chapter.
August 2014 2014.08.18 Initial release.
Level Two Title