3.5.18. Using altera_attribute to Set Quartus® Prime Logic Options

Quartus® Prime Standard Edition User Guide: Design Compilation

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3.5.18. Using altera_attribute to Set Quartus® Prime Logic Options

The altera_attribute attribute allows you to apply Quartus® Prime logic options and assignments to an object in your HDL source code. You can set this attribute on an entity, architecture, instance, register, RAM block, or I/O pin. You cannot set it on an arbitrary combinational node such as a net. With altera_attribute, you can control synthesis options from your HDL source even when the options lack a specific HDL synthesis attribute. You can also use this attribute to pass entity-level settings and assignments to phases of the Compiler flow that follow Analysis & Synthesis, such as Fitting.

Assignments or settings made through the Quartus® Prime software, the .qsf, or the Tcl interface take precedence over assignments or settings made with the altera_attribute synthesis attribute in your HDL code.

The attribute value is a single string containing a list of .qsf variable assignments separated by semicolons:

-name <variable_1> <value_1>;-name <variable_2> <value_2>[;…]

If the Quartus® Prime option or assignment includes a target, source, and section tag, you must use the syntax in this example for each .qsf variable assignment:

-name <variable> <value>
-from <source> -to <target> -section_id <section>

This example shows the syntax for the full attribute value, including the optional target, source, and section tags for two different .qsf assignments:

" -name <variable_1> <value_1> [-from <source_1>] [-to <target_1>] [-section_id \ <section_1>]; -name <variable_2> <value_2> [-from <source_2>] [-to <target_2>] \
[-section_id <section_2>] "

Table 63. Example UsageIf the assigned value of a variable is a string of text, you must use escaped quotes around the value in Verilog HDL or double-quotes in VHDL:
HDL	Code
Assigned Value of a Variable in Verilog HDL (With Nonexistent Variable and Value Terms)	"VARIABLE_NAME \"STRING_VALUE\""
Assigned Value of a Variable in VHDL (With Nonexistent Variable and Value Terms)	`"VARIABLE_NAME` ""STRING_VALUE"""

To find the .qsf variable name or value corresponding to a specific Quartus® Prime option or assignment, you can set the option setting or assignment in the Quartus® Prime software, and then make the changes in the .qsf.

Applying altera_attribute to an Instance

These examples use altera_attribute to set the power-up level of an inferred register.

Table 64. Applying altera_attribute to an InstanceThese examples use `altera_attribute` to set the power-up level of an inferred register.
HDL	Code
Verilog-1995	reg my_reg /* synthesis altera_attribute = "-name POWER_UP_LEVEL HIGH" */;
Verilog-2001	(* altera_attribute = "-name POWER_UP_LEVEL HIGH" *) reg my_reg;
VHDL	signal my_reg : std_logic; attribute altera_attribute : string; attribute altera_attribute of my_reg: signal is "-name POWER_UP_LEVEL HIGH";

Table 64. Applying altera_attribute to an InstanceThese examples use altera_attribute to set the power-up level of an inferred register.

HDL

Code

Verilog-1995

reg my_reg /* synthesis altera_attribute = "-name POWER_UP_LEVEL HIGH" */;

Verilog-2001

(* altera_attribute = "-name POWER_UP_LEVEL HIGH" *) reg my_reg;

VHDL

signal my_reg : std_logic;
attribute altera_attribute : string;
attribute altera_attribute of my_reg: signal is "-name POWER_UP_LEVEL HIGH";

Note: For inferred instances, you cannot apply the attribute to the instance directly. Therefore, you must apply the attribute to one of the output nets of the instance. The Quartus® Prime software automatically moves the attribute to the inferred instance.

Applying altera_attribute to an Entity

These examples use the altera_attribute to disable the Auto Shift Register Replacement synthesis option for an entity. To apply the Altera Attribute to a VHDL entity, you must set the attribute on its architecture rather than on the entity itself.

Table 65. Applying altera_attribute to an Entity
HDL	Code
Verilog-1995	module my_entity(…) /* synthesis altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" */;
Verilog-2001	(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) module my_entity(…) ;
VHDL	entity my_entity is -- Declare generics and ports end my_entity; architecture rtl of my_entity is attribute altera_attribute : string; -- Attribute set on architecture, not entity attribute altera_attribute of rtl: architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF"; begin -- The architecture body end rtl;

Table 65. Applying altera_attribute to an Entity

HDL

Code

Verilog-1995

module my_entity(…) /* synthesis altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" */;

Verilog-2001

(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) module my_entity(…) ;

VHDL

entity my_entity is
-- Declare generics and ports
end my_entity;
architecture rtl of my_entity is
attribute altera_attribute : string;
-- Attribute set on architecture, not entity
attribute altera_attribute of rtl: architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
begin
-- The architecture body
end rtl;

Applying altera_attribute with the -to Option

You can also use altera_attribute for more complex assignments that have more than one instance. In Table 66, the altera_attribute cuts all timing paths from reg1 to reg2, equivalent to this Tcl or .qsf command, as shown in the example below:

set_instance_assignment -name CUT ON -from reg1 -to reg2

Table 66. Applying altera_attribute with the -to Option
HDL	Code
Verilog-1995	reg reg2; reg reg1 /* synthesis altera_attribute = "-name CUT ON -to reg2" */;
Verilog-2001 and SystemVerilog	reg reg2; (* altera_attribute = "-name CUT ON -to reg2" *) reg reg1;
VHDL	signal reg1, reg2 : std_logic; attribute altera_attribute: string; attribute altera_attribute of reg1 : signal is "-name CUT ON -to reg2";

Table 66. Applying altera_attribute with the -to Option

HDL

Code

Verilog-1995

reg reg2;
reg reg1 /* synthesis altera_attribute = "-name CUT ON -to reg2" */;

Verilog-2001 and SystemVerilog

reg reg2;
(* altera_attribute = "-name CUT ON -to reg2" *) reg reg1;

VHDL

signal reg1, reg2 : std_logic;
attribute altera_attribute: string;
attribute altera_attribute of reg1 : signal is "-name CUT ON -to reg2";

You can specify either the -to option or the -from option in a single altera_attribute; Integrated Synthesis automatically sets the remaining option to the target of the altera_attribute. You can also specify wildcards for either option. For example, if you specify “*” for the -to option instead of reg2 in these examples, the Quartus® Prime software cuts all timing paths from reg1 to every other register in this design entity.

You can use the altera_attribute only for entity-level settings, and the assignments (including wildcards) apply only to the current entity.

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Quartus® Prime Standard Edition User Guide: Design Compilation

3.5.18. Using altera_attribute to Set Quartus® Prime Logic Options

Applying altera_attribute to an Instance

Applying altera_attribute to an Entity

Applying altera_attribute with the -to Option