3.8.5. Node-Naming Conventions for Combinational Logic Cells

Quartus® Prime Standard Edition User Guide: Design Compilation

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Date 10/22/2021

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3.8.5. Node-Naming Conventions for Combinational Logic Cells

Whenever possible for Verilog HDL, VHDL, and AHDL code, the Quartus® Prime software uses wire names that are the targets of assignments, but can change the node names due to synthesis optimizations.

For example, consider the Verilog HDL code in this example. Quartus® Prime Integrated Synthesis uses the names c, d, e, and f for the generated combinational logic cells.

wire c;
reg d, e, f;
assign c = a | b;
always @ (a or b)
d = a & b;
always @ (a or b) begin : my_label
e = a ^ b;
end
always @ (a or b)
f = ~(a | b);

For schematic designs using a .bdf, your design names all elements when you instantiate the elements in your design and the software uses the name you defined when possible.

If logic cells are packed with registers in device architectures such as the Stratix and Cyclone device families, those names might not appear in the netlist after fitting. In other devices, such as newer families in the Stratix and Cyclone series device families, the register and combinational nodes are kept separate throughout the compilation, so these names are more often maintained through fitting.

When logic optimizations occur during synthesis, it is not always possible to retain the initial names as described. Sometimes, synthesized names are used, which are the wire names with a tilde (~) and a number appended. For example, if a complex expression is assigned to wire w and that expression generates several logic cells, those cells can have names such as w, w~1, and w~2. Sometimes the original wire name w is removed, and an arbitrary name such as rtl~123 is created. Quartus® Prime Integrated Synthesis attempts to retain user names whenever possible. Any node name ending with ~<number> is a name created during synthesis, which can change if the design is changed and re-synthesized. Knowing these naming conventions helps you understand your post-synthesis results, helping you to debug your design or create assignments.

During synthesis, the software maintains combinational clock logic by not changing nodes that might be clocks. The software also maintains or protects multiplexers in clock trees, so that the Timing Analyzer has information about which paths are unate, to allow complete and correct analysis of combinational clocks. Multiplexers often occur in clock trees when the software selects between different clocks. To help with the analysis of clock trees, the software ensures that each multiplexer encountered in a clock tree is broken into 2:1 multiplexers, and each of those 2:1 multiplexers is mapped into one lookup table (independent of the device family). This optimization might result in a slight increase in area, and for some designs a decrease in timing performance. To disable the option, click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) > Clock MUX Protection.

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Quartus® Prime Standard Edition User Guide: Design Compilation

3.8.5. Node-Naming Conventions for Combinational Logic Cells