3.2.7.2. Passing Parameters Between Two Design Languages

Quartus® Prime Standard Edition User Guide: Design Compilation

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Date 10/22/2021

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3.2.7.2. Passing Parameters Between Two Design Languages

When passing a parameter between two different languages, a design block that is higher in the design hierarchy instantiates a lower-level subdesign block and provides parameter information. The subdesign language (the design entity that you instantiate) must correctly interpret the parameter. Based on the information provided by the higher-level design and the value format, and sometimes by the parameter type of the subdesign entity, the Quartus® Prime software interprets the type and value of the passed parameter.

When passing a parameter whose value is an enumerated type value or literal from a language that does not support enumerated types to one that does (for example, from Verilog HDL to VHDL), you must ensure that the enumeration literal is in the correct spelling in the language of the higher-level design block (block that is higher in the hierarchy). The Quartus® Prime software passes the parameter value as a string literal, and the language of the lower-level design correctly convert the string literal into the correct enumeration literal.

If the language of the lower-level entity is SystemVerilog, you must ensure that the enum value is in the correct case. In SystemVerilog, two enumeration literals differ in more than just case. For example, enum {item, ITEM} is not a good choice of item names because these names can create confusion and is more difficult to pass parameters from case-insensitive HDLs, such as VHDL.

Arrays have different support in different design languages. For details about the array parameter format, refer to the Parameter section in the Analysis & Synthesis Report of a design that contains array parameters or generics.

The following code shows examples of passing parameters from one design entry language to a subdesign written in another language.

Table 11. VHDL Parameterized Subdesign EntityThis table shows a VHDL subdesign that you instantiate in a top-level Verilog HDL design in Table 12.
HDL	Code
VHDL	type fruit is (apple, orange, grape); entity vhdl_sub is generic ( name : string := "default", width : integer := 8, number_string : string := "123", f : fruit := apple, binary_vector : std_logic_vector(3 downto 0) := "0101", signed_vector : signed (3 downto 0) := "1111");

Table 11. VHDL Parameterized Subdesign EntityThis table shows a VHDL subdesign that you instantiate in a top-level Verilog HDL design in Table 12.

HDL

Code

VHDL

type fruit is (apple, orange, grape);
entity vhdl_sub is
generic (
name : string := "default",
width : integer := 8,
number_string : string := "123",
f : fruit := apple,
binary_vector : std_logic_vector(3 downto 0) := "0101",
signed_vector : signed (3 downto 0) := "1111");

Table 12. Verilog HDL Top-Level Design Instantiating and Passing Parameters to VHDL EntityThis table shows a Verilog HDL Top-Level Design Instantiating and Passing Parameters to VHDL Entity from Table 11.
HDL	Code
Verilog HDL	vhdl_sub inst (...); defparam inst.name = "lower"; defparam inst.width = 3; defparam inst.num_string = "321"; defparam inst.f = "grape"; // Must exactly match enum value defparam inst.binary_vector = 4'b1010; defparam inst.signed_vector = 4'sb1010;

Table 12. Verilog HDL Top-Level Design Instantiating and Passing Parameters to VHDL EntityThis table shows a Verilog HDL Top-Level Design Instantiating and Passing Parameters to VHDL Entity from Table 11.

HDL

Code

Verilog HDL

vhdl_sub inst (...);
defparam inst.name = "lower";
defparam inst.width = 3;
defparam inst.num_string = "321";
defparam inst.f = "grape"; // Must exactly match enum value
defparam inst.binary_vector = 4'b1010;
      defparam inst.signed_vector = 4'sb1010;

Table 13. Verilog HDL Parameterized Subdesign ModuleThis table shows a Verilog HDL subdesign that you instantiate in a top-level VHDL design in Table 14.
HDL	Code
Verilog HDL	module veri_sub (...) parameter name = "default"; parameter width = 8; parameter number_string = "123"; parameter binary_vector = 4'b0101; parameter signed_vector = 4'sb1111;

Table 14. VHDL Top-Level Design Instantiating and Passing Parameters to the Verilog HDL ModuleThis table shows a VHDL Top-Level Design Instantiating and Passing Parameters to the Verilog HDL Module from Table 13.
HDL	Code
VHDL	inst:veri_sub generic map ( name => "lower", width => 3, number_string => "321" binary_vector = "1010" signed_vector = "1010")

To use an HDL subdesign such as the one shown in Table 13 in a top-level .bdf design, you must generate a symbol for the HDL file, as shown in Figure 34. Open the HDL file in the Quartus® Prime software, and then, on the File menu, point to Create/Update, and then click Create Symbol Files for Current File.

To specify parameters on a .bdf instance, double-click the parameter value box for the instance symbol, or right-click the symbol and click Properties, and then click the Parameters tab. Right-click the symbol and click Update Design File from Selected Block to pass the updated parameter to the HDL file.

Figure 34. BDF Top-Level Design Instantiating and Passing Parameters to the Verilog HDL ModuleThis figure shows BDF Top-Level Design Instantiating and Passing Parameters to the Verilog HDL Module from Table 13

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Quartus® Prime Standard Edition User Guide: Design Compilation

3.2.7.2. Passing Parameters Between Two Design Languages