3.5.12. Parallel Case

Quartus® Prime Standard Edition User Guide: Design Compilation

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Date 10/22/2021

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3.5.12. Parallel Case

The parallel_case attribute indicates that you must consider a Verilog HDL case statement as parallel; that is, you can match only one case item at a time. Case items in Verilog HDL case statements might overlap. To resolve multiple matching case items, the Verilog HDL language defines a priority among case items in which the case statement always executes the first case item that matches the case expression value. By default, the Quartus® Prime software implements the extra logic necessary to satisfy this priority relationship.

Attaching a parallel_case attribute to a case statement header allows the Quartus® Prime software to consider its case items as inherently parallel; that is, at most one case item matches the case expression value. Parallel case items simplify the generated logic.

In VHDL, the individual choices in a case statement might not overlap, so they are always parallel and this attribute does not apply.

Altera recommends that you use this attribute only when the case statement is truly parallel. If you use the attribute in any other situation, the generated logic does not match the functional simulation behavior of the Verilog HDL.

Note: Altera recommends that you avoid using the parallel_case attribute, because you may mismatch the Verilog HDL functional and the post- Quartus® Prime simulation.

If you specify SystemVerilog-2005 as the supported Verilog HDL version for your design, you can use the SystemVerilog keyword unique to achieve the same result as the parallel_case directive without causing simulation mismatches.

This example shows a casez statement with overlapping case items. In functional HDL simulation, the software prioritizes the three case items by the bits in sel. For example, sel[2] takes priority over sel[1], which takes priority over sel[0]. However, the synthesized design can simulate differently because the parallel_case attribute eliminates this priority. If more than one bit of sel is high, more than one output (a, b, or c) is high as well, a situation that cannot occur in functional HDL simulation.

Table 51. A `parallel_case` Attribute
HDL	Code
Verilog HDL	module parallel_case (sel, a, b, c); input [2:0] sel; output a, b, c; reg a, b, c; always @ (sel) begin {a, b, c} = 3'b0; casez (sel) // synthesis parallel_case 3'b1??: a = 1'b1; 3'b?1?: b = 1'b1; 3'b??1: c = 1'b1; endcase end endmodule

Table 51. A parallel_case Attribute

HDL

Code

Verilog HDL

module parallel_case (sel, a, b, c);
	input [2:0] sel;
	output a, b, c;
	reg a, b, c;
	always @ (sel)		
	begin
		{a, b, c} = 3'b0;
		casez (sel)		 // synthesis parallel_case
			3'b1??: a = 1'b1;
			3'b?1?: b = 1'b1;
			3'b??1: c = 1'b1;
		endcase
	end
endmodule

Table 52. Verilog-2001 SyntaxVerilog-2001 syntax also accepts the statements as shown in the following table in the `case` (or `casez`) header instead of the comment form, as shown in Table 51.
HDL	Syntax
Verilog-2001	(* parallel_case *) casez (sel)

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Quartus® Prime Standard Edition User Guide: Design Compilation

3.5.12. Parallel Case