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1.2.1. BMS Reference Design Software Requirements
1.2.2. BMS Reference Design Hardware Requirements
1.2.3. Downloading and Installing the BMS Reference Design
1.2.4. Setting Up the MAX 10 Development Board
1.2.5. Compiling the FPGA Hardware Design for the BMS Reference Design
1.2.6. Compiling the Nios Software for the BMS Reference Design
1.2.7. Programming the BMS Reference Design Hardware onto the Device
1.2.8. Downloading the BMS Reference Design Nios II Software to the Device
1.2.9. MATLAB Simulink Top-Level Design for the BMS Reference Design
1.2.10. Running the BMS Reference Design in a System-in-the-Loop Simulation
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1.4. BMS Reference Design FPGA Resource Usage
Use the resource usage to estimate the size of your design.
Component | LE | M9K | DSP |
---|---|---|---|
DEKF IP (design C only) | 20,610 | 30 | 29 |
Matrix processor (design B only) | 6,304 | 35 | 24 |
Nios II processor | 2,916 | 32 | 6 |
Nios II floating-point custom instruction core | 2,204 | 3 | 9 |
DDR controller | 4,785 | 12 | 0 |
Avalon-MM interconnect | 5,897 | 0 | 0 |
JTAG-Avalon-MM bridge | 799 | 1 | 0 |
Miscellaneous | 1,292 | 23 | 0 |
Design A total | ~14,000 | 57 | 15 |
Design B total | ~24,000 | 92 | 39 |
Design C total | ~33,000 | 84 | 35 |
Total | ~45,000/50,000 | 136/182 | 68 |