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Overview of the Design Security Feature
Hardware and Software Requirements
Steps for Implementing a Secure Configuration Flow
Steps to Enable Tamper-Protection Bit Programming
Supported Configuration Schemes
Security Mode Verification
Serial Flash Loader Support with Encryption Enabled
Serial Flash Loader Support with Encryption Enabled for Single FPGA Device Chain
JTAG Secure Mode for 28-nm and 20-nm FPGAs
Document Revision History for AN 556: Using the Design Security Features in Intel® FPGAs
Generating Single-Device .ekp File and Encrypting Configuration File using Intel® Quartus® Prime Software
Generating Single-Device .ekp File and Encrypting Configuration File using Command-Line Interface in Intel® Quartus® Prime Software
Generating Multi-Device .ekp File and Encrypting Configuration File using Intel® Quartus® Prime Software
Programming Volatile or Non-Volatile Key using Intel® FPGA Ethernet Cable and Intel® Quartus® Prime Software
Programming Single-Device Volatile or Non-Volatile Key using Intel® Quartus® Prime Software
Programming Single-Device Volatile or Non-Volatile Key using the Command-Line Interface in Intel® Quartus® Prime Software
Programming Multi-Device Volatile or Non-Volatile Key using Intel® Quartus® Prime Software
Programming Multi-Device Volatile or Non-Volatile Key using the Command-Line Interface in Intel® Quartus® Prime Software
Programming Key using JTAG Technologies
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Hardware Requirements
The following table lists the specifications that you must follow for a successful key programming.
Parameter | Key Programming Mode | |
---|---|---|
Non-Volatile Key | Volatile Key | |
TCK period | 10 µs ± 1 µs 11 | — |
Ambient Temperature | 25°C ± 5°C | 25°C ± 5°C |
Voltage (VCCBAT) | — | 12 |
VCCBAT is a dedicated power supply for the volatile key storage and is not shared with other on-chip power supplies, such as VCCIO or VCC. VCCBAT continuously supplies power to the volatile register regardless of the on-chip supply condition.
Note: After power up, you must wait for the device to exit power-on reset (POR) before beginning the key programming. You may encounter verification error when programming the volatile Encryption Key Programming (.ekp) file if you have the VCCBAT pin tied to GND. The VCCBAT pin must be tied to the recommended VCCBAT voltage provided in the respective device family pin connection guidelines for proper operation.
Related Information
11 Applies to 40-nm and 28-nm FPGAs only.
12 If you do not use the volatile key, refer to the respective device family pin connection guidelines for VCCBAT connection.