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Overview of the Design Security Feature
Hardware and Software Requirements
Steps for Implementing a Secure Configuration Flow
Steps to Enable Tamper-Protection Bit Programming
Supported Configuration Schemes
Security Mode Verification
Serial Flash Loader Support with Encryption Enabled
Serial Flash Loader Support with Encryption Enabled for Single FPGA Device Chain
JTAG Secure Mode for 28-nm and 20-nm FPGAs
Document Revision History for AN 556: Using the Design Security Features in Intel® FPGAs
Generating Single-Device .ekp File and Encrypting Configuration File using Intel® Quartus® Prime Software
Generating Single-Device .ekp File and Encrypting Configuration File using Command-Line Interface in Intel® Quartus® Prime Software
Generating Multi-Device .ekp File and Encrypting Configuration File using Intel® Quartus® Prime Software
Programming Volatile or Non-Volatile Key using Intel® FPGA Ethernet Cable and Intel® Quartus® Prime Software
Programming Single-Device Volatile or Non-Volatile Key using Intel® Quartus® Prime Software
Programming Single-Device Volatile or Non-Volatile Key using the Command-Line Interface in Intel® Quartus® Prime Software
Programming Multi-Device Volatile or Non-Volatile Key using Intel® Quartus® Prime Software
Programming Multi-Device Volatile or Non-Volatile Key using the Command-Line Interface in Intel® Quartus® Prime Software
Programming Key using JTAG Technologies
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Design Example Intel® Quartus® Prime Design Components
Component | Function and Description |
---|---|
JTAG_Lock_Unlock.bdf | The top entity of the reference design. |
JTAG_Lock_Unlock_wysiwyg.v | The Verilog code for the Arria V device WYSIWYG atom instantiation. You need to modify this code according to Table 18 for compliance with other 28-nm FPGAs. |
ALTINT_OSC.v | A IP core instantiation of an internal oscillator clock source. In this reference design, the clock source from the internal oscillator is used to drive the user logic to eliminate the need of an external clock source. |
User_logic_control_block.v | An example Verilog file that executes JTAG instructions using Arria V device WYSIWYG atom. You can modify this code to fit your design requirements and restrictions, or replace this code with another similar implementation. |
Pulse_nconfig.jam | Use this JAM file to execute the PULSE_NCONFIG JTAG instruction to verify the JTAG secure mode as shown in Verifying JTAG Secure Mode. This file is optional and can be replaced with other methods to verify the JTAG secure mode. |