DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683263
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. DMA Accelerator Functional Unit User Guide Archives 9. Document Revision History for the DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space
4. Software Programming Model x
4.1. Software APIs
4.1. Software APIs x
4.1.1. fpgaDmaOpen() 4.1.2. fpgaDmaTransferSync() 4.1.3. fpgaDmaClose()
5. Running DMA AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. DMA Accelerator Functional Unit User Guide Archives
9. Document Revision History for the DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

7. Simulating the AFU Example

Intel recommends you refer to the Intel Accelerator Functional Unit Simulation Environment Quick Start Guide for your Intel® PAC to be familiar with simulating similar examples and to setup your environment. Before you proceed through the following steps, verify that the OPAE_PLATFORM_ROOT environment variable is set to the OPAE SDK installation directory.

Complete the following steps to setup the hardware simulator for the DMA AFU:

  1. Change to the DMA AFU sample directory: 
    cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu
  2. Create an ASE environment in a new directory and configure it for simulating an AFU: 
    afu_sim_setup --source=./hw/rtl/filelist.txt  build_ase_dir
  3. Change to the ASE build directory: 
    cd build_ase_dir
  4. Build the driver and application: 
    make
  5. Make simulation: 
    make sim
Sample output from the hardware simulator: 
[SIM]  ** ATTENTION : BEFORE running the software application **
[SIM]  Set env(ASE_WORKDIR) in terminal where application will run (copy-and-paste) =>
[SIM]  $SHELL   | Run:
[SIM]  ---------+---------------------------------------------------
[SIM]  bash/zsh | export ASE_WORKDIR=/Tools/ias/inteldevstack/a10_gx_pac_ias_1_2_1_pv/hw/samples/dma_afu/build_ase_dir/work
[SIM]  tcsh/csh | setenv ASE_WORKDIR /Tools/ias/inteldevstack/a10_gx_pac_ias_1_2_1_pv/hw/samples/dma_afu/build_ase_dir/work
[SIM]  For any other $SHELL, consult your Linux administrator
[SIM]  
[SIM]  Ready for simulation...
[SIM]  Press CTRL-C to close simulator...
Complete the following steps to compile and execute the DMA AFU software in the simulation environment:
  1. Open a new terminal window.
  2. Change directory to:
    cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw
  3. Copy the environment setup string (choose string appropriate for your shell) from the steps above in the hardware simulation to the terminal window. See the following lines in the sample output from the hardware simulator.
    [SIM]  bash/zsh | export ASE_WORKDIR=/Tools/ias/inteldevstack/a10_gx_pac_ias_1_2_1_pv/hw/samples/dma_afu/build_ase_dir/work
[SIM]  tcsh/csh | setenv ASE_WORKDIR /Tools/ias/inteldevstack/a10_gx_pac_ias_1_2_1_pv/hw/samples/dma_afu/build_ase_dir/work
  4. Compile the software:
    make USE_ASE=1
  5. Execute the host application to transfer 4 KB in 1 KB portions from the host memory to the FPGA pattern checker:
    ./fpga_dma_test
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