DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683263
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. DMA Accelerator Functional Unit User Guide Archives 9. Document Revision History for the DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space
4. Software Programming Model x
4.1. Software APIs
4.1. Software APIs x
4.1.1. fpgaDmaOpen() 4.1.2. fpgaDmaTransferSync() 4.1.3. fpgaDmaClose()
5. Running DMA AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. DMA Accelerator Functional Unit User Guide Archives
9. Document Revision History for the DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

3.1. DMA AFU Register Map

The DMA register map provides the absolute addresses of all the locations within the unit. These registers are in the host view because it's only the host that can access them.

Table 4.  DMA AFU Memory Map
Byte Address Offsets Name Span in Bytes Description
0x0_0000 AFU DFH 8 Refer to Table 5 for the bit fields.
0x0_0008 AFU ID_L 8 Set to 0x9081F88B8F655CAA for the DMA AFU.
0x0_0010 AFU ID_H 8 Set to 0x331DB30C988541EA for the DMA AFU.
0x0_2000 MPF DFH 240 Specifies IDs, feature list, and control and status registers. The MPF decodes this information. This information is not available inside the DMA Platform Designer system.
0x2_0000 DMA BBB 8192 The DMA BBB memory map. Refer to Table 6 for the register offsets.

Table 5.  DMA AFU DFH Encoding
Bit Field Description
[11:0] Feature ID. Set to 0.
[15:12] AFU major revision number. Set to 0.
[39:16] Next DFH byte offset/DFH region size. Set to 8192.
[40] End of DFH list. When set, the DFH is at the end of the list. The default value is 0.
[47:41] Reserved.
[51:48] AFU minor revision number. Set to 0.
[59:52] Reserved.
[63:60] Feature type. Set to 1 (AFU).
Table 6.  DMA BBB Memory MapAdd the byte addresses below to the BBB DMA base address, 0x2_0000.
Byte Address Offsets Name Span in Bytes Description
0x0000 BBB DFH 8 Refer to Table 6 for the bit fields.
0x0008 BBB ID_L 8 Set to 0xA9149A35BACE01EA for the DMA BBB.
0x0010 BBB ID_H 8 Set to 0xEF82DEF7F6EC40FC for the DMA BBB.
0x0040 MSGDMA CSR 32 Controls the DMA.
0x0060 MSGDMA Descriptor 32 Receives DMA descriptors.
0x0200 Address Span Extender Control 8 Moves the address window that the data port accesses.
0x1000 Address Span Extender Data 4096 Maps a 4 KB window to a local device memory.
Table 7.  DMA BBB DFH Encoding
Bit Field Description
[11:0] Feature ID. Set to 0
[15:12] AFU major revision number. Set to 0.
[39:16] Next DFH byte offset / DFH region size. Set to 8192.
[40] End of DFH list. When set, the DFH is at the end of the list. The default value is 0.
[47:41] Reserved.
[51:48] AFU minor revision number. Set to 0
[59:52] Reserved.
[63:60] Feature type. Set to 2 (BBB).
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