Fault Injection Intel® FPGA IP Core User Guide

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ID 683254
Date 7/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Fault Injection Intel® FPGA IP Core User Guide
1. Fault Injection Intel® FPGA IP Core User Guide x
1.1. Features 1.2. Device Support 1.3. Resource Utilization and Performance 1.4. Installing and Licensing Intel® FPGA IP Cores 1.5. Customizing and Generating IP Cores 1.6. Functional Description 1.7. Using the Fault Injection Debugger and Fault Injection IP Core 1.8. Fault Injection IP Core User Guide Archives 1.9. Document Revision History for Fault Injection IP Core User Guide
1.5. Customizing and Generating IP Cores x
1.5.1. IP Catalog and Parameter Editor 1.5.2. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.6. Functional Description x
1.6.1. Single Event Upset Mitigation 1.6.2. Fault Injection IP Pin Description
1.7. Using the Fault Injection Debugger and Fault Injection IP Core x
1.7.1. Instantiating the Fault Injection IP Core 1.7.2. Defining Fault Injection Areas 1.7.3. Using the Fault Injection Debugger 1.7.4. Command-Line Interface
1.7.1. Instantiating the Fault Injection IP Core x
1.7.1.1. About the EMR Unloader IP Core 1.7.1.2. About the Advanced SEU Detection IP Core
1.7.2. Defining Fault Injection Areas x
1.7.2.1. Performing Hierarchy Tagging 1.7.2.2. About SMH Files
1.7.3. Using the Fault Injection Debugger x
1.7.3.1. Hardware and Software Requirements 1.7.3.2. Configuring Your Device and the Fault Injection Debugger 1.7.3.3. Constraining Regions for Fault Injection 1.7.3.4. Specifying Error Types 1.7.3.5. Injecting Errors 1.7.3.6. Recording Errors 1.7.3.7. Clearing Injected Errors
1.7.4. Command-Line Interface x
1.7.4.1. Targeted Fault Injection Feature 1.7.4.2. Advanced Command-Line Options: ASD Regions and Error Type Weighting
1.7.4.1. Targeted Fault Injection Feature x
1.7.4.1.1. Specifying an Error List From the Command Line 1.7.4.1.2. Specifying an Error List From Prompt Mode 1.7.4.1.3. Determining CRAM Bit Locations
1. Fault Injection Intel® FPGA IP Core User Guide

1.7. Using the Fault Injection Debugger and Fault Injection IP Core

The Fault Injection Debugger works together with the Fault Injection IP core. First, you instantiate the IP core in your design, compile, and download the resulting configuration file into your device. Then, you run the Fault Injection Debugger from within the Intel® Quartus® Prime software or from the command line to simulate soft errors.

  • The Fault Injection Debugger allows you to operate fault injection experiments interactively or by batch commands, and allows you to specify the logical areas in your design for fault injections.
  • The command-line interface is useful for running the debugger via a script.

The Fault Injection Debugger communicates with the Fault Injection IP core via the JTAG interface. The Fault Injection IP accepts commands from the JTAG interface and reports status back through the JTAG interface.

Note: The Fault Injection IP core is implemented in soft logic in your device; therefore, you must account for this logic usage in your design. One methodology is to characterize your design’s response to SEU in the lab and then omit the IP core from your final deployed design.

You use the Fault Injection IP core with the following IP cores:

  • The Error Message Register Unloader IP core, which reads and stores data from the hardened error detection circuitry in Intel FPGA devices.
  • (Optional) The Advanced SEU Detection Intel® FPGA IP core, which compares single-bit error locations to a sensitivity map during device operation to determine whether a soft error affects it.
Figure 5. Fault Injection Debugger Overview Block Diagram
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