Fault Injection Intel® FPGA IP Core User Guide

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ID 683254
Date 7/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Fault Injection Intel® FPGA IP Core User Guide
1. Fault Injection Intel® FPGA IP Core User Guide x
1.1. Features 1.2. Device Support 1.3. Resource Utilization and Performance 1.4. Installing and Licensing Intel® FPGA IP Cores 1.5. Customizing and Generating IP Cores 1.6. Functional Description 1.7. Using the Fault Injection Debugger and Fault Injection IP Core 1.8. Fault Injection IP Core User Guide Archives 1.9. Document Revision History for Fault Injection IP Core User Guide
1.5. Customizing and Generating IP Cores x
1.5.1. IP Catalog and Parameter Editor 1.5.2. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.6. Functional Description x
1.6.1. Single Event Upset Mitigation 1.6.2. Fault Injection IP Pin Description
1.7. Using the Fault Injection Debugger and Fault Injection IP Core x
1.7.1. Instantiating the Fault Injection IP Core 1.7.2. Defining Fault Injection Areas 1.7.3. Using the Fault Injection Debugger 1.7.4. Command-Line Interface
1.7.1. Instantiating the Fault Injection IP Core x
1.7.1.1. About the EMR Unloader IP Core 1.7.1.2. About the Advanced SEU Detection IP Core
1.7.2. Defining Fault Injection Areas x
1.7.2.1. Performing Hierarchy Tagging 1.7.2.2. About SMH Files
1.7.3. Using the Fault Injection Debugger x
1.7.3.1. Hardware and Software Requirements 1.7.3.2. Configuring Your Device and the Fault Injection Debugger 1.7.3.3. Constraining Regions for Fault Injection 1.7.3.4. Specifying Error Types 1.7.3.5. Injecting Errors 1.7.3.6. Recording Errors 1.7.3.7. Clearing Injected Errors
1.7.4. Command-Line Interface x
1.7.4.1. Targeted Fault Injection Feature 1.7.4.2. Advanced Command-Line Options: ASD Regions and Error Type Weighting
1.7.4.1. Targeted Fault Injection Feature x
1.7.4.1.1. Specifying an Error List From the Command Line 1.7.4.1.2. Specifying an Error List From Prompt Mode 1.7.4.1.3. Determining CRAM Bit Locations
1. Fault Injection Intel® FPGA IP Core User Guide

1.6.2. Fault Injection IP Pin Description

The Fault Injection IP core includes the following I/O pins.

Table 4.   Fault Injection IP Core I/O Pins

Pin Name

Pin Direction

Pin Description

crcerror_pin

input

Input from Error Message Register Unloader Intel® FPGA IP (EMR Unloader IP). This signal is asserted when a CRC error has been detected by the device's EDCRC.

emr_data input

Error Message Register (EMR) contents. Refer to the appropriate device handbook for the EMR fields.

This input complies with the Avalon Streaming data interface signal.

emr_valid

input

Indicates the emr_data inputs contain valid data. This is an Avalon Streaming valid interface signal.
Reset

input

Module reset input. The reset is fully controlled by the Fault Injection Debugger.

error_injected

output

Indicates an error was injected into CRAM as commanded via the JTAG interface. The length of time this signal asserts depends on your settings of the JTAG TCK and control block signals. Typically, the time is around 20 clock cycles of the TCK signal.

error_scrubbed

output

Indicates the device scrubbing is complete as commanded via the JTAG interface. The length of time this signal asserts depends on your settings of the JTAG TCK and control block signals. Typically, the time is around 20 clock cycles of the TCK signal.

intosc

output

Optional output. The Fault Injection IP uses this clock, for example, to clock the EMR_unloader block.
Figure 4.  Fault Injection IP Pin Diagram
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