25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683252
Date 6/18/2020
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Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Quick Start Guide 2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices 5. 25G Ethernet Intel® FPGA IP Design Example References 6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. 25G Ethernet Intel® FPGA IP Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench x
1.3.1. Procedure
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure
1.5. Changing Target Device in Hardware Design Example x
1.5.1. Procedure
1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware x
1.6.1. Procedure
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 2.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
2.6. Hardware Testing x
2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature 2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Compilation 3.6. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
3.6. Hardware Testing x
3.6.1. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Compilation 4.6. Hardware Testing
4.3. Functional Description x
4.3.1. Design Components
4.4. Simulation x
4.4.1. Testbench 4.4.2. Simulation Design Example Components 4.4.3. Test Case
4.6. Hardware Testing x
4.6.1. Test Procedure
5. 25G Ethernet Intel® FPGA IP Design Example References x
5.1. Design Example Interface Signals 5.2. Design Example Registers 5.3. Using Transceiver Toolkit on H-Tile Production Device
1. 25G Ethernet Intel® FPGA IP Quick Start Guide
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
5. 25G Ethernet Intel® FPGA IP Design Example References
6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

4.4.3. Test Case

The simulation test case performs the following steps:

  1. Instantiates 25G Ethernet Intel® FPGA IP and ATX PLL.
  2. Waits for PHY status signal to settle.
  3. Prints PHY status.
  4. Analyzes the results. The successful testbench sends and receives packets, and displays "Testbench complete."
Figure 23. Sample Simulation Output when Ethernet Channel is Configured to 1This figure shows a successful simulation test run when the Ethernet channel (i.e., LINK) is configured to 1.
Figure 24. Sample Simulation Output when Ethernet Channel is Configured to 4 (Part 1 of 2)This figure shows a successful simulation test run when the Ethernet channel (i.e., LINK) is configured to 4.
Figure 25. Sample Simulation Output when Ethernet Channel is Configured to 4 (Part 2 of 2)This figure shows a successful simulation test run when the Ethernet channel (i.e., LINK) is configured to 4.
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