25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683252
Date 6/18/2020
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Quick Start Guide 2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices 4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices 5. 25G Ethernet Intel® FPGA IP Design Example References 6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. 25G Ethernet Intel® FPGA IP Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench x
1.3.1. Procedure
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure
1.5. Changing Target Device in Hardware Design Example x
1.5.1. Procedure
1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware x
1.6.1. Procedure
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 2.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
2.6. Hardware Testing x
2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature 2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Compilation 3.6. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
3.6. Hardware Testing x
3.6.1. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Compilation 4.6. Hardware Testing
4.3. Functional Description x
4.3.1. Design Components
4.4. Simulation x
4.4.1. Testbench 4.4.2. Simulation Design Example Components 4.4.3. Test Case
4.6. Hardware Testing x
4.6.1. Test Procedure
5. 25G Ethernet Intel® FPGA IP Design Example References x
5.1. Design Example Interface Signals 5.2. Design Example Registers 5.3. Using Transceiver Toolkit on H-Tile Production Device
1. 25G Ethernet Intel® FPGA IP Quick Start Guide
2. 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
3. 25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
5. 25G Ethernet Intel® FPGA IP Design Example References
6. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

3.3.1. Design Components

Table 8.  Design Components
Component Description
25G Ethernet Intel® FPGA IP

Consists of MAC, PCS, and Transceiver PHY, with the following configuration:

  • Core Variant: MAC+PCS+PMA, MAC+PCS
  • Enable flow control: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable statistics collection: Optional
  • Enable MAC statistics counters: Optional
  • Enable 10G/25G dynamic rate switching: Not selected
  • Enable Native PHY Debug Master Endpoint (NPDME): Optional
  • Reference clock frequency: 644.531250/322.265625
For the design example with the IEEE 1588 feature, the following additional parameters are configured:
  • Enable IEEE 1588: Selected
  • Time of day format: Enable 96-bit timestamp format 2
For the design example with the RS-FEC feature, the following additional parameter is configured:
  • Enable RS-FEC: Selected
ATX PLL Generates TX serial clocks for the 25G transceiver.
Client logic Consists of:
  • Traffic generator, which generates burst packets to the 25G Ethernet Intel® FPGA IP core for transmission.
  • Traffic monitor, which monitors burst packets that are coming from the 25G Ethernet Intel® FPGA IP core.
Source and Probe Source and probe signals, including system reset input signal, which you can use for debugging.
Design Components for the IEEE 1588v2 Feature
Sampling PLL Generates the clocks for the IEEE 1588v2 design components.
  • latency_sclk: 156.25 MHz for latency measurement.
  • sampling_clk: 250 MHz for ToD synchronization
Time-of-day (ToD) Sync Synchronizes the 25G ToD.
ToD Tx ToD for transmit paths for the 25G transceiver.
ToD Rx ToD for receive paths for the 25G transceiver.
Master Precision Time Protocol (PTP) Master PTP consists of a packet generator and a packet receiver.
  • Packet generator: Obtains timestamp information from the 25G Ethernet Intel® FPGA IP core and generates Avalon® streaming packets such as Sync packet and Delay Response packet.
  • Packet receiver: Obtains the delay request packet information from the 25G Ethernet Intel® FPGA IP core and produces timestamp values.
Slave PTP Slave PTP consists of a packet generator, a packet receiver, and a packet compute.
  • Packet generator: Obtains timestamp information from the 25G Ethernet Intel® FPGA IP core and generates Avalon® streaming packets such as Delay Request packet.
  • Packet receiver: Obtains the Sync and Delay Response packets information from the 25G Ethernet Intel® FPGA IP core and produces timestamp values.
  • Packet compute: Calculates and produces the delay and offsets value based on the timestamp values.
2 The 25G Ethernet single-channel design example with IEEE 1588v2 feature only supports 96-bit timestamp format.
Level Two Title