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1.1. Block-Based Design Terminology
1.2. Block-Based Design Overview
1.3. Design Methodologies Overview
1.4. Design Partitioning
1.5. Design Block Reuse Flows
1.6. Incremental Block-Based Compilation Flow
1.7. Combining Design Block Reuse and Incremental Block-Based Compilation
1.8. Setting-Up Team-Based Designs
1.9. Bottom-Up Design Considerations
1.10. Debugging Block-Based Designs with the Signal Tap Logic Analyzer
1.11. Block-Based Design Flows Revision History
1.12. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
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1.6.2.1. Empty Partition Clock Source Preservation
Empty partitions preserve clock sources that the Intel® Quartus® Prime software recognizes.
The Intel® Quartus® Prime software recognizes and preserves the following as clock sources for a partition:
- Signals from a PLL.
- Feeds from internal clock inputs on flip-flops, memories, HSSIO, I/O registers, or PLLs outside the partition that you empty.
The Intel® Quartus® Prime software does not recognize the following as clock sources for a partition:
- Nets with sources external to the FPGA that do not feed a clock input inside the FPGA.
- Nets that connect only to combinatorial logic.
- Nets that connect only to an output pin.
- Nets that feed only logic within an empty partition.