Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design

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ID 683247
Date 12/16/2019
Public

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Document Table of Contents
Document Table of Contents x
1. Block-Based Design Flows A. Intel® Quartus® Prime Pro Edition User Guides
1. Block-Based Design Flows x
1.1. Block-Based Design Terminology 1.2. Block-Based Design Overview 1.3. Design Methodologies Overview 1.4. Design Partitioning 1.5. Design Block Reuse Flows 1.6. Incremental Block-Based Compilation Flow 1.7. Combining Design Block Reuse and Incremental Block-Based Compilation 1.8. Setting-Up Team-Based Designs 1.9. Bottom-Up Design Considerations 1.10. Debugging Block-Based Designs with the Signal Tap Logic Analyzer 1.11. Block-Based Design Flows Revision History 1.12. Intel® Quartus® Prime Pro Edition User Guide: Block-Based Design Document Archive
1.2. Block-Based Design Overview x
1.2.1. Design Block Reuse Overview 1.2.2. Incremental Block-Based Compilation Overview
1.2.1. Design Block Reuse Overview x
1.2.1.1. Design Block Reuse Examples
1.2.2. Incremental Block-Based Compilation Overview x
1.2.2.1. Incremental Block-Based Compilation Examples
1.3. Design Methodologies Overview x
1.3.1. Top-Down Design Methodology Overview 1.3.2. Bottom-Up Design Methodology Overview 1.3.3. Team-Based Design Methodology Overview
1.4. Design Partitioning x
1.4.1. Planning Partitions for Periphery IP, Clocks, and PLLs 1.4.2. Design Partition Guidelines 1.4.3. Partition Snapshot Preservation and Reuse 1.4.4. Creating Design Partitions
1.5. Design Block Reuse Flows x
1.5.1. Reusing Core Partitions 1.5.2. Reusing Root Partitions 1.5.3. Reserved Core Entity Re-Binding 1.5.4. Viewing Quartus Database File Information
1.5.1. Reusing Core Partitions x
1.5.1.1. Step 1: Developer: Create a Design Partition 1.5.1.2. Step 2: Developer: Compile and Export the Core Partition 1.5.1.3. Step 3: Developer: Create a Black Box File 1.5.1.4. Step 4: Consumer: Add the Core Partition and Compile
1.5.2. Reusing Root Partitions x
1.5.2.1. Step 1: Developer: Create a Reserved Core Partition 1.5.2.2. Step 2: Developer: Define a Logic Lock Region 1.5.2.3. Step 3: Developer: Compile and Export the Root Partition 1.5.2.4. Step 4: Consumer: Add the Root Partition and Compile
1.5.4. Viewing Quartus Database File Information x
1.5.4.1. QDB File Attribute Types
1.6. Incremental Block-Based Compilation Flow x
1.6.1. Incremental Timing Closure 1.6.2. Design Abstraction
1.6.1. Incremental Timing Closure x
1.6.1.1. Incremental Timing Closure Recommendations and Limitations
1.6.2. Design Abstraction x
1.6.2.1. Empty Partition Clock Source Preservation
1.8. Setting-Up Team-Based Designs x
1.8.1. Creating a Top-Level Project for a Team-Based Design
1.8.1. Creating a Top-Level Project for a Team-Based Design x
1.8.1.1. Prepare a Design Partition for Project Integration
1. Block-Based Design Flows
A. Intel® Quartus® Prime Pro Edition User Guides

1.11. Block-Based Design Flows Revision History

Document Version Intel® Quartus® Prime Version Changes
2019.12.16 19.4.0
  • Updated for cross-device snapshot reuse support and limits throughout.
2019.11.11 19.2.0
  • Described Fast Preserve option in "Block-Based Design Terminology" and "Step 4: Add the Root Partition and Compile."
2019.07.15 19.2.0
  • Changed default file export location from output_files to project directory.
  • Updated description of partition type GUI.
  • Updated Support for "Combined Incremental Block-Based Compilation and Design Block Reuse" table for latest supported combinations.
  • Added note about merging partitions to "Creating Design Partitions."
2018.10.01 18.1.0
  • Removed reference to Placed snapshot from "Step 3: Compile and Export the Root Partition." Only Synthesized and Final snapshots are supported for design block reuse.
2018.09.24 18.1.0
  • Reorganized order of topics in chapter.
  • Added the following new topics:
    • Viewing Quartus Database File Information
    • Reserved Core Entity Re-Binding
    • Incremental Block-Based Compilation Examples
    • Design Methodologies
    • Top-Down Design Methodology Overview
    • Bottom-Up Design Methodology Overview
    • Bottom-Up Design Recommendations and Limitations
    • Team-Based Design Methodology Overview
    • Incremental Timing Closure
    • Incremental Timing Closure Recommendations and Limitations
    • Design Abstraction
  • Replaced references to "periphery reuse core" with "reserved core" to reflect latest GUI.
  • Added description of | as root partition hierarchy path in Design Partitions Window.
  • Replaced details in "Debugging Block-Based Designs with the Signal Tap Logic Analyzer" section with link to AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board.
  • Minor wording and graphic updates throughout.
  • Removed references to unsupported Planned snapshot.
2018.05.07 18.0.0
  • First release of chapter as part of stand-alone Block-Based Design User Guide.
  • Added footnote and links to known issues.
  • Updated all design flow steps to match current GUI.
  • Updated description of Include entity-bound SDC files option.
  • Updated statement defining parent to child partition attribute inheritance.
  • Added Design Partition Settings topic.
  • Added Block-Based Design Terminology topic.
  • Added Preservation and Reuse with Compiler Snapshots topic.
  • Added Empty Partition Clock Source Preservation topic.
  • Added Design Partitions Properties table.
  • Added Combining Incremental Block-Based Compilation and Design Block Reuse topic.
  • Updated Debugging Block-Based Designs topic and linked to new Application Note.
2017.11.06 17.1.0
  • Reorganization of introduction and Incremental Block-Based Compilation.
  • Added Design Partitioning section.
  • Added Debugging Block-Based Designs section.
  • Added Use Empty Partitions to Reduce Compilation Time topic.
  • Removed requirement to add .psmf, .msf, and .sof to Consumer project.
  • Added Intel® Stratix® 10 support, including information about bundling of .sdc with exported partitions for Intel® Stratix® 10 designs.
  • Documented changes to Design Partitions window, Export Design Partition dialog box, and Logic Lock Regions window.
  • Added reference to new Design Partition Planner.
  • Updated references to corresponding .qsf assignments.
  • Changed references from periphery reuse to root partition reuse.
  • Rebranded for latest Intel® standards.
2017.05.08 17.0.0
  • First public release.
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