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1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
3.1. Memory Block Types
3.2. Write and Read Operations Triggering
3.3. Port Width Configurations
3.4. Mixed-width Port Configuration
3.5. Mixed-width Ratio Configuration
3.6. Maximum Block Depth Configuration
3.7. Clocking Modes and Clock Enable
3.8. Memory Blocks Address Clock Enable Support
3.9. Byte Enable
3.10. Asynchronous Clear
3.11. Read Enable
3.12. Read-During-Write
3.13. Power-Up Conditions and Memory Initialization
3.14. Error Correction Code
3.15. Freeze Logic
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3.2. Write and Read Operations Triggering
The embedded memory blocks vary slightly in its supported features and behaviors. One important variation is the difference in the write and read operations triggering.
| Embedded Memory Blocks | Write Operation | Read Operation |
|---|---|---|
| M10K | Rising clock edges | Rising clock edges |
| M20K | Rising clock edges | Rising clock edges |
| M144K | Rising clock edges | Rising clock edges |
| M9K | Rising clock edges | Rising clock edges |
| MLAB | Falling clock edges Rising clock edges (in Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V devices only) |
Rising clock edges 3 |
| M-RAM | Rising clock edges | Rising clock edges |
| M4K | Falling clock edges | Rising clock edges |
| M512 | Falling clock edges | Rising clock edges |
It is important that you understand the write operation triggering to avoid potential write contentions that can result in unknown data storage at that location.
These figures show the valid write operation that triggers at the rising and falling clock edge, respectively.
Figure 1. Valid Write Operation that Triggers at Rising Clock EdgesThis figure assumes that twc is the maximum write cycle time interval. Write operation of data 03 through port B does not meet the criteria and causes write contention with the write operation at port A, which result in unknown data at address 01. The write operation at the next rising edge is valid because it meets the criteria and data 04 replaces the unknown data.
Figure 2. Valid Write Operation that Triggers at Falling Clock Edges This figure assumes that twc is the maximum write cycle time interval. Write operation of data 04 through port B does not meet the criteria and therefore causes write contention with the write operation at port A that result in unknown data at address 01. The next data (05) is latched at the next rising clock edge that meets the criteria and is written into the memory block at the falling clock edge.
Note: Data and addresses are latched at the rising edge of the write clock regardless of the different write operation triggering.
2 Write operation triggering is not applicable to ROMs.
3 MLAB supports continuos reads. For example, when you write a data at the write clock rising edge and after the write operation is complete, you see the written data at the output port without the need for a read clock rising edge.