Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

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ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

6. Design Example

Simulate the designs using the ModelSim* - Intel® FPGA Edition software to generate a waveform display of the device behavior.

The following design files in Internal_Memory_DesignExample.zip:

  • ecc_encoder.v
  • ecc_decoder.v
  • true_dp_ram.v
  • top_dpram.v
  • true_dp_ram.vt
  • true_dp.do
  • true_dp_ram.qar ( Intel® Quartus® Prime design file)

Section Content
External ECC Implementation with True-Dual-Port RAM

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