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1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
3.1. Memory Block Types
3.2. Write and Read Operations Triggering
3.3. Port Width Configurations
3.4. Mixed-width Port Configuration
3.5. Mixed-width Ratio Configuration
3.6. Maximum Block Depth Configuration
3.7. Clocking Modes and Clock Enable
3.8. Memory Blocks Address Clock Enable Support
3.9. Byte Enable
3.10. Asynchronous Clear
3.11. Read Enable
3.12. Read-During-Write
3.13. Power-Up Conditions and Memory Initialization
3.14. Error Correction Code
3.15. Freeze Logic
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3.6. Maximum Block Depth Configuration
You can limit the maximum block depth of the dedicated memory block you use.
The memory block can be sliced to your desired maximum block depth. For example, the capacity of an M9K block is 9,216 bits, and the default memory depth is 8K, in which each address is capable of storing 1 bit (8K × 1). If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 × 18).
You can use this option to save power usage in your devices. However, this parameter might increase the number of LEs and affects the design performance.
When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower slices.
You can also use this option to reduce the total number of memory blocks used (but at the expense of LEs). The 8K × 36 RAM uses 36 M9K RAM blocks with a default slicing of 8K × 1. By setting the maximum block depth to 1K, the 8K × 36 RAM can fit into 32 M9K blocks.
The maximum block depth must be in a power of two, and the valid values vary among different dedicated memory blocks.
| Embedded Memory Blocks | Valid Range |
|---|---|
| M10K | 256–8K |
| M20K | 512–16K |
| M144K | 2K–16K |
| M9K | 256–8K |
| MLAB | 32–64 5 |
| M512 | 32–512 |
| M4K | 128–4K |
| M-RAM | 4K–64K |
The parameter editor prompts an error message if you enter an invalid value for the maximum block depth. Intel® recommends that you set the value to Auto if you are not sure of the appropriate maximum block depth to set or the setting is not important for your design. This setting enables the compiler to select the maximum block depth with the appropriate port width configuration for the type of embedded memory block of your memory.
4 The maximum block depth must be in a power of two.
5 The maximum block depth setting (64) for MLAB is not available for Arria® V and Cyclone® V devices.