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1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
3.1. Memory Block Types
3.2. Write and Read Operations Triggering
3.3. Port Width Configurations
3.4. Mixed-width Port Configuration
3.5. Mixed-width Ratio Configuration
3.6. Maximum Block Depth Configuration
3.7. Clocking Modes and Clock Enable
3.8. Memory Blocks Address Clock Enable Support
3.9. Byte Enable
3.10. Asynchronous Clear
3.11. Read Enable
3.12. Read-During-Write
3.13. Power-Up Conditions and Memory Initialization
3.14. Error Correction Code
3.15. Freeze Logic
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2. Embedded Memory IP Cores Getting Started
This chapter provides a general overview of the Intel® FPGA IP core design flow to help you quickly get started with the Embedded Memory IP cores. The Intel® FPGA IP Library is installed as part of the Intel® Quartus® Prime software installation process. You can select and parameterize any Intel® FPGA IP core from the library. Intel provides an integrated parameter editor that allows you to customize the Embedded Memory IP cores to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports.