Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Compilation 3. Reducing Compilation Time 4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Compilation x
2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Netlist Infrastructure (Beta) 2.4. Design Synthesis 2.5. Design Place and Route 2.6. Incremental Optimization Flow 2.7. Fast Forward Compilation Flow 2.8. Full Compilation Flow 2.9. Exporting Compilation Results 2.10. Integrating Other EDA Tools 2.11. Synthesis Language Support 2.12. Compiler Optimization Techniques 2.13. Synthesis Settings Reference 2.14. Fitter Settings Reference 2.15. Design Compilation Revision History
2.1. Compilation Overview x
2.1.1. Compilation Flows 2.1.2. Compilation Hierarchy 2.1.3. Compilation Monitoring
2.3. Design Netlist Infrastructure (Beta) x
2.3.1. Exploring the RTL Analyzer (Beta) 2.3.2. Early Timing Analysis After Design Synthesis (Beta) 2.3.3. DNI Use Case Examples
2.3.1. Exploring the RTL Analyzer (Beta) x
2.3.1.1. Sweep Hints Viewer 2.3.1.2. Connectivity Tracer 2.3.1.3. Object Set Console 2.3.1.4. Module Interfaces 2.3.1.5. Bundled Instances 2.3.1.6. Auto-hide Unconnected Pins 2.3.1.7. Filtering Ports and Nets 2.3.1.8. Expand Connections
2.3.2. Early Timing Analysis After Design Synthesis (Beta) x
2.3.2.1. Synopsys* Design Constraint (SDC) on RTL 2.3.2.2. Post-Synthesis Static Timing Analysis (STA) 2.3.2.3. Types of SDC Files Used in the Intel® Quartus® Prime Software
2.3.2.1. Synopsys* Design Constraint (SDC) on RTL x
2.3.2.1.1. Registering the SDC-on-RTL SDC File 2.3.2.1.2. Applying the SDC-on-RTL Constraints 2.3.2.1.3. Inspecting SDC-on-RTL Constraints 2.3.2.1.4. Creating Constraints in SDC-on-RTL SDC Files
2.3.3. DNI Use Case Examples x
2.3.3.1. Scripting Routine Tasks Using DNI Tcl Commands 2.3.3.2. Traversing the DNI Netlist Using Tcl Commands
2.4. Design Synthesis x
2.4.1. Running Synthesis 2.4.2. Viewing Synthesis Reports 2.4.3. Viewing Synthesis Dynamic Report
2.4.1. Running Synthesis x
2.4.1.1. Preserving Registers During Synthesis 2.4.1.2. Preserving Signals for Monitoring and Debugging
2.5. Design Place and Route x
2.5.1. Running the Fitter 2.5.2. Viewing Fitter Reports
2.5.1. Running the Fitter x
2.5.1.1. Fitter Commands 2.5.1.2. Disabling or Enabling Physical Synthesis Optimization
2.5.2. Viewing Fitter Reports x
2.5.2.1. Plan Stage Reports 2.5.2.2. Place Stage Reports 2.5.2.3. Route Stage Reports 2.5.2.4. Retime Stage Reports 2.5.2.5. Finalize Stage Reports
2.5.2.2. Place Stage Reports x
2.5.2.2.1. Global Signal Visualization Report
2.5.2.3. Route Stage Reports x
2.5.2.3.1. Global Router Congestion Hotspot Summary Report 2.5.2.3.2. Global Router Wire Utilization Map Report
2.6. Incremental Optimization Flow x
2.6.1. Concurrent Analysis During Synthesis or Fitting 2.6.2. Analyzing Compiler Snapshots 2.6.3. Validating Periphery (I/O) after the Plan Stage
2.6.2. Analyzing Compiler Snapshots x
2.6.2.1. Running Snapshot Viewer
2.6.2.1. Running Snapshot Viewer x
2.6.2.1.1. Analyzing Failing Paths with Snapshot Viewer 2.6.2.1.2. Analyzing Clocking with Snapshot Viewer 2.6.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 2.6.2.1.4. Validating Timing Constraints with Snapshot Viewer 2.6.2.1.5. Analyzing Congestion with Snapshot Viewer
2.7. Fast Forward Compilation Flow x
2.7.1. Step 1: Run Register Retiming 2.7.2. Step 2: Review Retiming Results 2.7.3. Step 3: Run Fast Forward Compile 2.7.4. Step 4: Review Fast Forward Results 2.7.5. Step 5: Implement Fast Forward Recommendations 2.7.6. Retiming Restrictions and Workarounds
2.7.2. Step 2: Review Retiming Results x
2.7.2.1. Locate Critical Chains
2.7.3. Step 3: Run Fast Forward Compile x
2.7.3.1. Fast Forward Compile By Hierarchy 2.7.3.2. HyperFlex Settings
2.7.4. Step 4: Review Fast Forward Results x
2.7.4.1. Clock Fmax Summary Report 2.7.4.2. Fast Forward Details Report
2.8. Full Compilation Flow x
2.8.1. Full Compilation Flow with Temporary Optimization Mode
2.9. Exporting Compilation Results x
2.9.1. Exporting a Version-Compatible Compilation Database 2.9.2. Importing a Version-Compatible Compilation Database 2.9.3. Creating a Design Partition 2.9.4. Exporting a Design Partition Manual Design Partition Export Automated Design Partition Export 2.9.5. Reusing a Design Partition 2.9.6. Viewing Quartus Database File Information 2.9.7. Clearing Compilation Results
2.9.6. Viewing Quartus Database File Information x
2.9.6.1. QDB File Attribute Types
2.10. Integrating Other EDA Tools x
2.10.1. Generating a VQM Netlist for other EDA Tools
2.11. Synthesis Language Support x
2.11.1. Verilog and SystemVerilog Synthesis Support 2.11.2. VHDL Synthesis Support
2.11.1. Verilog and SystemVerilog Synthesis Support x
2.11.1.1. Verilog HDL Input Settings (Settings Dialog Box) 2.11.1.2. Design Libraries 2.11.1.3. Verilog HDL Configuration 2.11.1.4. Initial Constructs and Memory System Tasks 2.11.1.5. Verilog HDL Macros
2.11.1.3. Verilog HDL Configuration x
2.11.1.3.1. Hierarchical Design Configurations
2.11.2. VHDL Synthesis Support x
2.11.2.1. VHDL Input Settings (Settings Dialog Box) 2.11.2.2. VHDL Standard Libraries and Packages 2.11.2.3. VHDL wait Constructs 2.11.2.4. VHDL-2019 Conditional Analysis Tool Directives
2.12. Compiler Optimization Techniques x
2.12.1. Compiler Optimization Modes 2.12.2. Allow Register Retiming 2.12.3. Automatic Gated Clock Conversion 2.12.4. Enable Intermediate Fitter Snapshots 2.12.5. Fast Preserve Option 2.12.6. Fractal Synthesis Optimization
2.12.6. Fractal Synthesis Optimization x
2.12.6.1. Enabling or Disabling Fractal Synthesis
2.13. Synthesis Settings Reference x
2.13.1. Advanced Synthesis Settings
3. Reducing Compilation Time x
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
3.2. Strategies to Reduce the Overall Compilation Time x
3.2.1. Running the ECO Compilation Flow 3.2.2. Enabling Multi-Processor Compilation 3.2.3. Using Block-Based Compilation
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
3.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 3.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
3.4. Reducing Placement Time x
3.4.1. Placement Effort Multiplier Settings
3.5. Reducing Routing Time x
3.5.1. Identifying Routing Congestion with the Chip Planner
3.5.1. Identifying Routing Congestion with the Chip Planner x
3.5.1.1. Areas with Routing Congestion 3.5.1.2. Congestion due to HDL Coding style
1. Answers to Top FAQs
2. Design Compilation
3. Reducing Compilation Time
4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.9.4. Exporting a Design Partition

The following steps describe export of design partitions that you create in your project.

When you compile a design containing design partitions, the Compiler can preserve a synthesis or final snapshot of results for each partition. You can export the synthesized or final compilation results for individual design partitions with the Export Design Partition dialog box.

If the partition includes any entity-bound .sdc files, you can include those constraints in the .qdb. In addition, you can automate export of one or more partitions in the Design Partitions Window.

Manual Design Partition Export

Follow these steps to manually export a design partition with the Export Design Partition dialog box:

  1. Open a project and create one or more design partitions. Creating a Design Partition describes this process.
  2. Run synthesis (Processing > Start > Start Analysis & Synthesis) or full compilation (Processing > Start Compilation), depending on which compilation results that you want to export.
  3. Click Project > Export Design Partition, and specify one or more options in the Export Design Partition dialog box:
    Figure 98. Export Design Partition Dialog Box
    • Select the Partition name and the compilation Snapshot for export.
    • To include any entity-bound .sdc files in the exported .qdb, turn on Include entity-bound SDC files for the selected partition.
  4. Click OK. The compilation results for the design partition exports to the file that you specify.

Automated Design Partition Export

Follow these steps to automatically export one or more design partitions following each compilation:

  1. Open a project containing one or more design partitions. Creating a Design Partition describes this process.
  2. To open the Design Partitions Window, click Assignments > Design Partitions Window.
  3. To automatically export a partition with synthesis results after each time you run synthesis, specify the a .qdb export path and file name for the Post Synthesis Export File option for that partition. If you specify only a file name without a path, the file exports to the output_files directory after compilation.
  4. To automatically export a partition with final snapshot results each time you run the Fitter, specify a .qdb file name for the Post Final Export File option for that partition. If you specify only a file name without a path, the file exports to the output_files directory after compilation.
Figure 99. Specifying Export File in Design Partitions Window

.qsf Equivalent Assignment: 

set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_<FINAL|SYNTHESIZED> \
     <hpath> -to <file_name>.qdb
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