Visible to Intel only — GUID: epa1471043689354
Ixiasoft
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives
11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency 40G for ASIC Proto Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. TX PCS Interface to User Logic
6.4. RX PCS Interface to User Logic
6.5. Transceivers Signals
6.6. Transceiver Reconfiguration Signals
6.7. Avalon® Memory-Mapped Management Interface
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
6.10. Clocks
6.11. Flow Control Interface
Visible to Intel only — GUID: epa1471043689354
Ixiasoft
3.6.1. Understanding the Testbench Behavior
The testbenches send traffic through the IP core in transmit-to-receive loopback mode, exercising the transmit side and receive side of the IP core in the same data flow. These testbenches send traffic to allow the Ethernet lanes to lock, and then send packets to the transmit client data interface and check the data as it returns through the receive client data interface.
The Low Latency 40G for ASIC Proto Ethernet IP core implements virtual lanes as defined in the IEEE 802.3ba-2012 Ethernet Standard. The IP core is fixed at four virtual lanes; the four virtual lanes are typically transmitted over four 10 Gbps physical lanes. When the lanes arrive at the receiver the lane streams are in an undefined order. Each lane carries a periodic PCS-VLANE alignment tag to restore the original ordering. The simulation establishes a random permutation of the physical lanes that is used for the remainder of the simulation.
Within each virtual lane stream, the data is 64B/66B encoded. Each word has two framing bits which are always either 01 or 10, never 00 or 11. The RX logic uses this pattern to lock onto the correct word boundaries in each serial stream. The process is probabilistic due to false locks on the pseudo-random scrambled stream.
Both the word lock and the alignment marker lock implement hysteresis as defined in the IEEE Standard for Ethernet, Section 4. Multiple successes are required to acquire lock and multiple failures are required to lose lock. The “fully locked” messages in the simulation log indicate the point at which a physical lane has successfully identified the word boundary and virtual lane assignment.
In the event of a catastrophic error, the RX PCS automatically attempts to reacquire alignment. The MAC properly identifies errors in the datastream.