Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide

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ID 683221
Date 11/10/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP 2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives 11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP x
1.1. Low Latency 40G for ASIC Proto Ethernet IP Core Supported Features 1.2. Device Family Support 1.3. Low Latency 40G for ASIC Proto Ethernet IP Core Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Low Latency 40G for ASIC Proto Ethernet IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the Transceiver PLL 3.5.3. Adding the External TX MAC PLL 3.5.4. Placement Settings for the Low Latency 40G for ASIC Proto Ethernet Core
3.6. Low Latency 40G for ASIC Proto Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G for ASIC Proto Ethernet Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Low Latency 40G for ASIC Proto Ethernet Core Functional Description x
4.1.1. Low Latency 40G for ASIC Proto Ethernet Core TX MAC Datapath 4.1.2. Low Latency 40G for ASIC Proto Ethernet Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Flow Control
4.1.1. Low Latency 40G for ASIC Proto Ethernet Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion
4.1.2. Low Latency 40G for ASIC Proto Ethernet Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.1.4. Flow Control x
4.1.4.1. TX Pause/PFC Flow Control Transmission 4.1.4.2. XON/XOFF Pause Frames
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. TX PCS Interface to User Logic 6.4. RX PCS Interface to User Logic 6.5. Transceivers Signals 6.6. Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Statistics Registers
7.4. Statistics Registers x
7.4.1. TX Statistics Registers 7.4.2. RX Statistics Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP
2. Low Latency 40G for ASIC Proto Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide Archives
11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History

6.3. TX PCS Interface to User Logic

The Low Latency 40G for ASIC Proto Ethernet IP core TX client interface in PCS Only variations employs the Media Independent Interface (MII) protocol.

The client acts as a source and the TX PCS acts as a sink in the transmit direction.

Table 15.  Signals of the MII TX Client Interface

Signal Name

Description

clk_txmac The TX clock for the IP core is clk_txmac. The frequency of this clock is 312.5 MHz.

If you turn on Use external TX MAC PLL parameter, the clk_txmac_in input clock drives clk_txmac.

tx_mii_d[127:0]

TX MII input data from MAC to PCS. Data must be in MII encoding.

The IP core handles two data blocks per clock cycle.

tx_mii_c[15:0]

TX MII control bits. Each bit corresponds to a byte of i_tx_mii_d. i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0], i_tx_mii_c[1] corresponds to i_tx_mii_d[15:8], and so on.

The IP core handles two data blocks per clock cycle.

tx_mii_valid Indicates that tx_mii_d is valid.

You must assert this signal a fixed number of clock cycles after the IP core raises tx_mii_ready, and must deassert this signal the same number of clock cycles after the IP core deasserts tx_mii_ready. The number must be in the range of 1–10 clock cycles.

While you hold the value of this signal at 0, you must freeze the values of both tx_mii_d and tx_mii_c stable.

tx_mii_ready Indicates the PCS is ready to receive new data.
tx_pcs_am Alignment marker insertion bit. You must hold this signal asserted for 2 clk_txmac consecutive clock cycles, counting only the valid cycles, to drive the insertion of an alignment marker. A valid cycle is one in which tx_mii_valid has the value of 1.

The number of valid clock cycles from deassertion of tx_pcs_am (alignment marker insertion bit signal) to reassertion of tx_pcs_am is the am_period.

  • For normal operation of the Ethernet link, you must ensure that the value of am_period is 32766 clock cycles. .
  • In simulation you can reduce this value to 510. This change decreases the simulation time to RX PCS alignment. You can set the IP core to expect this interval by setting the sim_mode RTL parameter to Enable.
    Note: The value for the MAC+PCS variations is different, to ensure the value on the internal signal has the appropriate am_period.

For an example that handles this setting for simulation and drives the tx_pcs_am signal appropriately for simulation, refer to the IP core design example for PCS Only variations. For information about how to generate the IP core design example, refer to the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide. For information about the sim_mode RTL parameter, refer to the RTL Parameters section of this user guide.

While you hold the value of this signal at 1, you must freeze the values of both tx_mii_d and tx_mii_c.

Figure 17. TX MII Client Interface for Low Latency 40G for ASIC Proto Ethernet IP Core
Figure 18. Alignment Marker Insertion on the TX MII Client Interface
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