Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide

ID 683221
Date 11/10/2022
Public
Document Table of Contents

11. Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Revision History

Date Intel® Quartus® Prime Version IP Version Changes
2020.10.05 20.3 19.1.0
  • Revised Select USER MAC mode parameter options:
    • Updated from PHY+MAC+PCS to PCS+MAC.
    • Updated from PHY+PCS to PCS_Only.
  • Revised the Flow Control Signals table to update the following signal description:
    • pause_insert_tx0[(FCQN-1):0]
    • pause_insert_tx1[(FCQN-1):0]
    • pause_insert_rx[(FCQN-1):0]
  • Added new section: Ethernet Toolkit Overview.
2020.07.07 20.2 19.1.0 Initial release.