Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP User Guide

ID 683221
Date 11/10/2022
Public
Document Table of Contents

1.4. Resource Utilization

Resource utilization changes depending on the parameter settings you specify in the Low Latency 40G for ASIC Proto Ethernet parameter editor. For example, if you turn on statistics counters in the Low Latency 40G for ASIC Proto Ethernet parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 5.  IP Core Options Encoding for Resource Utilization Table"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
MAC + PCS IP Core Variation A B C D E F
Parameter
Ready latency 0 0 3 3 3 0
Use external TX MAC PLL On On
Enable TX CRC insertion On On On On
Enable link fault generation On
Enable preamble passthrough On
Enable MAC stats counters On On On On
Table 6.  IP Core FPGA Resource UtilizationLists the resources and expected performance for selected variations of the Low Latency 40G for ASIC Proto Ethernet IP core in an Intel® Stratix® 10 device.

These results were obtained using the Intel® Quartus® Prime 20.2 software version.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus Prime Fitter Report.

IP Core Variation

ALMs

Dedicated Logic Registers

Memory

M20K

A 6,900 16,500 1
B 10,700 24,800 1
C 11,400 26,800 1
D 11,100 25,500 1
E 11,100 26,000 1
F 3,000 7,100 1