External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

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ID 683216
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP 2. Intel® Agilex™ FPGA EMIF IP – Introduction 3. Intel® Agilex™ FPGA EMIF IP – Product Architecture 4. Intel® Agilex™ FPGA EMIF IP – End-User Signals 5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support 7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support 8. Intel® Agilex™ FPGA EMIF IP – Timing Closure 9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure 10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization 11. Intel® Agilex™ FPGA EMIF IP – Debugging 12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives 13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP x
1.1. Release Information
2. Intel® Agilex™ FPGA EMIF IP – Introduction x
2.1. Intel® Agilex™ EMIF IP Protocol and Feature Support 2.2. Intel® Agilex™ EMIF IP Design Flow 2.3. Intel® Agilex™ EMIF IP Design Checklist
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture x
3.1. Intel® Agilex™ EMIF Architecture: Introduction 3.2. Intel® Agilex™ EMIF Sequencer 3.3. Intel® Agilex™ EMIF Calibration 3.4. Intel® Agilex™ EMIF Controller 3.5. User-requested Reset in Intel® Agilex™ EMIF IP 3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem 3.7. Using a Custom Controller with the Hard PHY
3.1. Intel® Agilex™ EMIF Architecture: Introduction x
3.1.1. Intel® Agilex™ EMIF Architecture: I/O Subsystem 3.1.2. Intel® Agilex™ EMIF Architecture: I/O SSM 3.1.3. Intel® Agilex™ EMIF Architecture: I/O Bank 3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane 3.1.5. Intel® Agilex™ EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel® Agilex™ EMIF Architecture: PHY Clock Tree 3.1.7. Intel® Agilex™ EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel® Agilex™ EMIF Architecture: Clock Phase Alignment
3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane x
3.1.4.1. Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme
3.3. Intel® Agilex™ EMIF Calibration x
3.3.1. Intel® Agilex™ Calibration Stages 3.3.2. Intel® Agilex™ Calibration Stages Descriptions 3.3.3. Intel® Agilex™ Calibration Flowchart 3.3.4. Intel® Agilex™ Calibration Algorithms
3.3.4. Intel® Agilex™ Calibration Algorithms x
3.3.4.1. Calibration Algorithms for DDR4 3.3.4.2. Calibration Algorithms for QDR-IV 3.3.4.3. Guidelines for Debugging Calibration Issues
3.3.4.1. Calibration Algorithms for DDR4 x
3.3.4.1.1. DDR4 Read Calibration 3.3.4.1.2. DDR4 Write Calibration
3.3.4.2. Calibration Algorithms for QDR-IV x
3.3.4.2.1. QDR-IV Read Calibration 3.3.4.2.2. QDR-IV Write Calibration
3.3.4.3. Guidelines for Debugging Calibration Issues x
3.3.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 3.3.4.3.2. Debugging Address and Command Leveling Calibration Failure 3.3.4.3.3. Debugging Address and Command Deskew Failure 3.3.4.3.4. Debugging DQS Enable Failure 3.3.4.3.5. Debugging Read Deskew Calibration Failure 3.3.4.3.6. Debugging VREFIN Calibration Failure 3.3.4.3.7. Debugging LFIFO Calibration Failure 3.3.4.3.8. Debugging Write Leveling Failure 3.3.4.3.9. Debugging Write Deskew Calibration Failure 3.3.4.3.10. Debugging VREFOUT Calibration Failure
3.4. Intel® Agilex™ EMIF Controller x
3.4.1. Hard Memory Controller 3.4.2. Intel® Agilex™ Hard Memory Controller Rate Conversion Feature
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features 3.4.1.2. Hard Memory Controller Main Control Path 3.4.1.3. Data Buffer Controller
3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem x
3.6.1. Restrictions on I/O Bank Usage for Intel® Agilex™ EMIF IP with HPS
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals x
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions 4.2. Intel® Agilex™ EMIF IP AFI Signals 4.3. Intel® Agilex™ EMIF IP AFI 4.0 Timing Diagrams 4.4. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions x
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 x
4.1.1.1. local_reset_req for DDR4 4.1.1.2. local_reset_status for DDR4 4.1.1.3. pll_ref_clk for DDR4 4.1.1.4. pll_locked for DDR4 4.1.1.5. ac_parity_err for DDR4 4.1.1.6. oct for DDR4 4.1.1.7. mem for DDR4 4.1.1.8. status for DDR4 4.1.1.9. afi_reset_n for DDR4 4.1.1.10. afi_clk for DDR4 4.1.1.11. afi_half_clk for DDR4 4.1.1.12. afi for DDR4 4.1.1.13. emif_usr_reset_n for DDR4 4.1.1.14. emif_usr_clk for DDR4 4.1.1.15. ctrl_amm for DDR4 4.1.1.16. ctrl_amm_aux for DDR4 4.1.1.17. ctrl_auto_precharge for DDR4 4.1.1.18. ctrl_user_priority for DDR4 4.1.1.19. ctrl_ecc_user_interrupt for DDR4 4.1.1.20. ctrl_ecc_readdataerror for DDR4 4.1.1.21. ctrl_ecc_status for DDR4 4.1.1.22. ctrl_mmr_slave for DDR4 4.1.1.23. hps_emif for DDR4 4.1.1.24. emif_calbus for DDR4 4.1.1.25. emif_calbus_clk for DDR4
4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV x
4.1.2.1. local_reset_req for QDR-IV 4.1.2.2. local_reset_status for QDR-IV 4.1.2.3. pll_ref_clk for QDR-IV 4.1.2.4. pll_locked for QDR-IV 4.1.2.5. oct for QDR-IV 4.1.2.6. mem for QDR-IV 4.1.2.7. status for QDR-IV 4.1.2.8. afi_reset_n for QDR-IV 4.1.2.9. afi_clk for QDR-IV 4.1.2.10. afi_half_clk for QDR-IV 4.1.2.11. afi for QDR-IV 4.1.2.12. emif_usr_reset_n for QDR-IV 4.1.2.13. emif_usr_clk for QDR-IV 4.1.2.14. ctrl_amm for QDR-IV 4.1.2.15. emif_calbus for QDR-IV 4.1.2.16. emif_calbus_clk for QDR-IV
4.2. Intel® Agilex™ EMIF IP AFI Signals x
4.2.1. AFI Clock and Reset Signals 4.2.2. AFI Address and Command Signals 4.2.3. AFI Write Data Signals 4.2.4. AFI Read Data Signals 4.2.5. AFI Calibration Status Signals 4.2.6. AFI Tracking Management Signals 4.2.7. AFI Shadow Register Management Signals
4.3. Intel® Agilex™ EMIF IP AFI 4.0 Timing Diagrams x
4.3.1. AFI Address and Command Timing Diagrams 4.3.2. AFI Write Sequence Timing Diagrams 4.3.3. AFI Read Sequence Timing Diagrams 4.3.4. AFI Calibration Status Timing Diagram
4.4. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables x
4.4.1. ctrlcfg0 4.4.2. ctrlcfg1 4.4.3. dramtiming0 4.4.4. sbcfg1 4.4.5. caltiming0 4.4.6. caltiming1 4.4.7. caltiming2 4.4.8. caltiming3 4.4.9. caltiming4 4.4.10. caltiming9 4.4.11. dramaddrw 4.4.12. sideband0 4.4.13. sideband1 4.4.14. sideband4 4.4.15. sideband6 4.4.16. sideband7 4.4.17. sideband9 4.4.18. sideband11 4.4.19. sideband12 4.4.20. sideband13 4.4.21. sideband14 4.4.22. dramsts 4.4.23. niosreserve0 4.4.24. niosreserve1 4.4.25. sideband16 4.4.26. ecc3: ECC Error and Interrupt Configuration 4.4.27. ecc4: Status and Error Information 4.4.28. ecc5: Address of Most Recent SBE/DBE 4.4.29. ecc6: Address of Most Recent Correction Command Dropped 4.4.30. ecc7: Extension for Address of Most Recent SBE/DBE 4.4.31. ecc8: Extension for Address of Most Recent Correction Command Dropped
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Options 5.2. Simulation Walkthrough
5.2. Simulation Walkthrough x
5.2.1. Calibration Modes 5.2.2. Simulation Scripts 5.2.3. Functional Simulation with Verilog HDL 5.2.4. Functional Simulation with VHDL 5.2.5. Simulating the Design Example
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support x
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 6.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 6.3. Register Map IP-XACT Support for Intel® Agilex™ EMIF DDR4 IP 6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 6.5. DDR4 Board Design Guidelines
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
6.1.1. Intel Agilex EMIF IP DDR4 Parameters: General 6.1.2. Intel Agilex EMIF IP DDR4 Parameters: Memory 6.1.3. Intel Agilex EMIF IP DDR4 Parameters: Mem I/O 6.1.4. Intel Agilex EMIF IP DDR4 Parameters: FPGA I/O 6.1.5. Intel Agilex EMIF IP DDR4 Parameters: Mem Timing 6.1.6. Intel Agilex EMIF IP DDR4 Parameters: Controller 6.1.7. Intel Agilex EMIF IP DDR4 Parameters: Diagnostics 6.1.8. Intel Agilex EMIF IP DDR4 Parameters: Example Designs
6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 6.4.2. Intel® Agilex™ FPGA EMIF IP Resources 6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
6.4.1.1. Estimating Pin Requirements 6.4.1.2. DIMM Options 6.4.1.3. Maximum Number of Interfaces
6.4.2. Intel® Agilex™ FPGA EMIF IP Resources x
6.4.2.1. OCT 6.4.2.2. PLL
6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
6.4.3.1. Intel® Agilex™ FPGA EMIF IP Banks 6.4.3.2. General Guidelines 6.4.3.3. x4 DIMM Implementation 6.4.3.4. Specific Pin Connection Requirements 6.4.3.5. Command and Address Signals 6.4.3.6. Clock Signals 6.4.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.5. DDR4 Board Design Guidelines x
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices 6.5.2. Clamshell Topology 6.5.3. General Layout Routing Guidelines 6.5.4. Reference Stackup 6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies 6.5.7. Intel® Agilex™ EMIF Pin Swapping Guidelines
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices x
6.5.1.1. Dynamic On-Chip Termination (OCT) 6.5.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.5.1.3. Choosing Terminations on Intel® Agilex™ FPGA Devices 6.5.1.4. On-Chip Termination Recommendations for Intel® Agilex™ FPGA Devices
6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.5.5.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, LRDIMM, and SODIMM DDR4 Topologies 6.5.5.2. Two DIMMs per Channel (2DPC) for UDIMM, RDIMM, and LRDIMM DDR4 Topologies 6.5.5.3. Two DIMMs per Channel (2DPC) for SODIMM Topology 6.5.5.4. Skew Matching Guidelines for DIMM Configurations 6.5.5.5. Power Delivery Recommendations for the Memory / DIMM Side
6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.5.6.1. Single Rank x 8 Discrete (Component) Topology 6.5.6.2. Single Rank x 16 Discrete (Component) Topology 6.5.6.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and R Rank x 16 Discrete (Component) Topologies 6.5.6.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.5.6.5. Power Delivery Recommendations for DDR4 Discrete Configurations
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support x
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 7.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 7.4. QDR-IV Board Design Guidelines
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
7.1.1. Intel Agilex EMIF IP QDR-IV Parameters: General 7.1.2. Intel Agilex EMIF IP QDR-IV Parameters: Memory 7.1.3. Intel Agilex EMIF IP QDR-IV Parameters: FPGA I/O 7.1.4. Intel Agilex EMIF IP QDR-IV Parameters: Mem Timing 7.1.5. Intel Agilex EMIF IP QDR-IV Parameters: Controller 7.1.6. Intel Agilex EMIF IP QDR-IV Parameters: Diagnostics 7.1.7. Intel Agilex EMIF IP QDR-IV Parameters: Example Designs
7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 7.3.2. Intel® Agilex™ FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. Maximum Number of Interfaces
7.3.2. Intel® Agilex™ FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
7.3.3.1. Intel® Agilex™ FPGA EMIF IP Banks 7.3.3.2. General Guidelines 7.3.3.3. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 7.3.3.4. QDR IV SRAM Clock Signals 7.3.3.5. QDR IV SRAM Data, DINV, and QVLD Signals 7.3.3.6. Specific Pin Connection Requirements 7.3.3.7. Resource Sharing Guidelines (Multiple Interfaces)
7.4. QDR-IV Board Design Guidelines x
7.4.1. General Layout Routing Guidelines 7.4.2. Reference Stackup 7.4.3. Routing Guidelines for QDR-IV Topology 7.4.4. Intel® Agilex™ EMIF Design Guideline Summary
7.4.3. Routing Guidelines for QDR-IV Topology x
7.4.3.1. QDR-IV Single Device Memory Topology 7.4.3.2. Skew Matching Guidelines for QDR-IV Configurations 7.4.3.3. Power Delivery Recommendation for QDR-IV Configurations
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure x
8.1. Timing Closure 8.2. Optimizing Timing
8.1. Timing Closure x
8.1.1. Timing Analysis
8.1.1. Timing Analysis x
8.1.1.1. PHY or Core
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure x
9.1. I/O Timing Closure Overview 9.2. Collateral Generated with Your EMIF IP 9.3. SPICE Decks 9.4. File Organization 9.5. Top-level Parameterization File 9.6. IP-Supplied Parameters that You Might Need to Override 9.7. Understanding the *_ip_parameters.dat File and Making a Mask Polygon 9.8. Multi-Rank Topology 9.9. Pin Parasitics 9.10. Mask Evaluation
9.3. SPICE Decks x
9.3.1. Address/Command Simulation Deck 9.3.2. FPGA Write Operation Simulation Deck 9.3.3. FPGA Read Operation Simulation Deck
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Auto-Precharge Commands 10.4.2. Additive Latency 10.4.3. Bank Interleaving 10.4.4. Additive Latency and Bank Interleaving 10.4.5. User-Controlled Refresh 10.4.6. Frequency of Operation 10.4.7. Series of Reads or Writes 10.4.8. Data Reordering 10.4.9. Starvation Control 10.4.10. Command Reordering 10.4.11. Bandwidth 10.4.12. Enable Command Priority Control 10.4.13. Controller Pre-pay and Post-pay Refresh (DDR4 Only)
10.4.1. Auto-Precharge Commands x
10.4.1.1. Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces
11. Intel® Agilex™ FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Hardware Debugging Guidelines 11.6. Categorizing Hardware Issues 11.7. Debugging with the External Memory Interface Debug Toolkit 11.8. Using the Default Traffic Generator 11.9. Using the Configurable Traffic Generator (TG2) 11.10. EMIF On-Chip Debug Port 11.11. Efficiency Monitor
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages 11.2.4. Modifying the Example Driver to Replicate the Failure
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer x
11.4.1. Signals to Monitor with the Signal Tap Logic Analyzer
11.5. Hardware Debugging Guidelines x
11.5.1. Create a Simplified Design that Demonstrates the Same Issue 11.5.2. Measure Power Distribution Network 11.5.3. Measure Signal Integrity and Setup and Hold Margin 11.5.4. Vary Voltage 11.5.5. Operate at a Lower Speed 11.5.6. Determine Whether the Issue Exists in Previous Versions of Software 11.5.7. Determine Whether the Issue Exists in the Current Version of Software 11.5.8. Try A Different PCB 11.5.9. Try Other Configurations 11.5.10. Debugging Checklist
11.6. Categorizing Hardware Issues x
11.6.1. Signal Integrity Issues 11.6.2. Hardware and Calibration Issues
11.6.1. Signal Integrity Issues x
11.6.1.1. Characteristics of Signal Integrity Issues 11.6.1.2. Evaluating Signal Integrity Issues
11.6.1.2. Evaluating Signal Integrity Issues x
11.6.1.2.1. Skew 11.6.1.2.2. Crosstalk 11.6.1.2.3. Power System 11.6.1.2.4. Clock Signals 11.6.1.2.5. Address and Command Signals 11.6.1.2.6. Read Data Valid Window and Eye Diagram 11.6.1.2.7. Write Data Valid Window and Eye Diagram 11.6.1.2.8. OCT and ODT Usage
11.6.2. Hardware and Calibration Issues x
11.6.2.1. Postamble Timing Issues and Margin 11.6.2.2. Intermittent Issue Evaluation 11.6.2.3. Memory Timing Parameter Evaluation 11.6.2.4. Verify that the Board Has the Correct Memory Component or DIMM Installed
11.7. Debugging with the External Memory Interface Debug Toolkit x
11.7.1. Prerequisites for Using the EMIF Debug Toolkit 11.7.2. Configuring a Design to Use the Toolkit 11.7.3. Launching the EMIF Debug Toolkit 11.7.4. Using the EMIF Debug Toolkit 11.7.5. Exporting Tables 11.7.6. Viewing Reports Graphically in the Eye Viewer
11.7.2. Configuring a Design to Use the Toolkit x
11.7.2.1. Generating a Design Example with the Debug Toolkit 11.7.2.2. Creating a Design Example with Multiple External Memory Interfaces 11.7.2.3. Enabling the EMIF Toolkit in an Existing Design
11.7.4. Using the EMIF Debug Toolkit x
11.7.4.1. Memory Configuration Tab 11.7.4.2. Calibration Tab 11.7.4.3. Guidelines for Debugging Calibration Issues 11.7.4.4. Calibration Report Tab 11.7.4.5. Calibrate Termination Tab 11.7.4.6. Vref Margining Tab 11.7.4.7. Driver Margining Tab 11.7.4.8. ISSPs Tab 11.7.4.9. Pin Delay Settings Tab
11.7.4.2. Calibration Tab x
11.7.4.2.1. Rerunning Calibration 11.7.4.2.2. Rerunning the Traffic Generator
11.7.4.3. Guidelines for Debugging Calibration Issues x
11.7.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 11.7.4.3.2. Debugging Address and Command Leveling Calibration Failure 11.7.4.3.3. Debugging Address and Command Deskew Failure 11.7.4.3.4. Debugging DQS Enable Failure 11.7.4.3.5. Debugging Read Deskew Calibration Failure 11.7.4.3.6. Debugging VREFIN Calibration Failure 11.7.4.3.7. Debugging LFIFO Calibration Failure 11.7.4.3.8. Debugging Write Leveling Failure 11.7.4.3.9. Debugging Write Deskew Calibration Failure 11.7.4.3.10. Debugging VREFOUT Calibration Failure
11.8. Using the Default Traffic Generator x
11.8.1. Reading the Default Traffic Generator Status 11.8.2. Running Infinite Traffic using the Default Traffic Generator 11.8.3. Changing the Reset Trigger of the Default Traffic Generator 11.8.4. Observing Generated Traffic with Signal Tap
11.9. Using the Configurable Traffic Generator (TG2) x
11.9.1. Enabling the Traffic Generator in a Design Example 11.9.2. Traffic Generator Block Description 11.9.3. Default Traffic Pattern 11.9.4. Configuration and Status Registers 11.9.5. User Pattern 11.9.6. Traffic Generator Status 11.9.7. Starting Traffic with the Traffic Generator 11.9.8. Traffic Generator Configuration User Interface
11.9.5. User Pattern x
11.9.5.1. Test Duration / Instruction pattern 11.9.5.2. Address Pattern 11.9.5.3. Data Pattern and Byte Enable
11.9.5.2. Address Pattern x
11.9.5.2.1. Address Generator Modes 11.9.5.2.2. Address Generator MSB Indices 11.9.5.2.3. Address Generator Effective Width 11.9.5.2.4. Address Generator Relative Frequencies 11.9.5.2.5. Address Pattern Examples - Basic Mode 11.9.5.2.6. Address Pattern Examples - Advanced Mode
11.9.8. Traffic Generator Configuration User Interface x
11.9.8.1. Connecting the Traffic Generator 11.9.8.2. Configuring the Traffic Generator 11.9.8.3. Traffic Generator Preset Selection 11.9.8.4. Traffic Generator Status Report 11.9.8.5. Examples of Configuring the TG2 Traffic Generator
11.10. EMIF On-Chip Debug Port x
11.10.1. Enabling the On-Chip Debug Port 11.10.2. I/O SSM calbus Bridge Data Structures and Usage 11.10.3. I/O SSM User-RAM Data Structures and Usage 11.10.4. Debug Interface Structure 11.10.5. Example: Reading Calibration Results and Margins with the On-Chip Debug Port
11.10.3. I/O SSM User-RAM Data Structures and Usage x
11.10.3.1. Parameter Tables 11.10.3.2. Parameter Table Enums
11.10.3.1. Parameter Tables x
11.10.3.1.1. Global Parameter Table 11.10.3.1.2. Per-interface Parameter Table Structure 11.10.3.1.3. Parameter Table Arrays
11.10.4. Debug Interface Structure x
11.10.4.1. Debug Data Structures 11.10.4.2. Debug Enums
11.11. Efficiency Monitor x
11.11.1. Enabling the Efficiency Monitor in a Design Example 11.11.2. Efficiency Monitor Block Descriptions 11.11.3. Control and Status Registers 11.11.4. Opening the Efficiency Monitor Toolkit
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP
2. Intel® Agilex™ FPGA EMIF IP – Introduction
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization
11. Intel® Agilex™ FPGA EMIF IP – Debugging
12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives
13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

11.10.5. Example: Reading Calibration Results and Margins with the On-Chip Debug Port

This example provides instructions for reading calibration results and margins using the on-chip debug port.

The values in the example below are for illustrative purposes and are obtained from an EMIF example design using DDR4 RDIMM x72, implemented on the Intel® Agilex™ F-Series FPGA Development Kit.

  1. Assume that you obtain the following data from the Global Parameter Table (GPT):
    Address Field Name Value
    0x500_0000 gpt_GLOBAL_PAR_VER 0x00000002
    0x500_0004 gpt_NIOS_C_VER 0x00000001
    0x500_0008 gpt_COLUMN_ID 0x00000001
    0x500_000c gpt_NUM_IOPACKS 0x00000010
    0x500_0010 gpt_NIOS_CLK_FREQ_KHZ 0x0003D090
    0x500_0014 gpt_PARAM_TABLE_SIZE 0x000001A0
    0x500_0018 gpt_RESERVED 0x00000008
    0x500_001c gpt_GLOBAL_CAL_CONFIG 0x00000505
    0x500_0020 gpt_SLAVE_CLK_DIVIDER 0x0000001C
    0x500_0024 gpt_INTERFACE_PAR_PTRS_0 0x00000064
    0x500_0028 gpt_INTERFACE_PAR_PTRS_1 0x00000000
    0x500_002c gpt_INTERFACE_PAR_PTRS_2 0x00000000
    0x500_0030 gpt_INTERFACE_PAR_PTRS_3 0x00000000
    0x500_0034 gpt_INTERFACE_PAR_PTRS_4 0x00000000
    0x500_0038 gpt_INTERFACE_PAR_PTRS_5 0x00000000
    0x500_003c gpt_INTERFACE_PAR_PTRS_6 0x00000000
    0x500_0040 gpt_INTERFACE_PAR_PTRS_7 0x00000000
    0x500_0044 gpt_INTERFACE_PAR_PTRS_8 0x00000000
    0x500_0048 gpt_INTERFACE_PAR_PTRS_9 0x00000000
    0x500_004c gpt_INTERFACE_PAR_PTRS_10 0x00000000
    0x500_0050 gpt_INTERFACE_PAR_PTRS_11 0x00000000
    0x500_0054 gpt_INTERFACE_PAR_PTRS_12 0x00000000
    0x500_0058 gpt_INTERFACE_PAR_PTRS_13 0x00000000
    0x500_005c gpt_INTERFACE_PAR_PTRS_14 0x00000000
    0x500_0060 gpt_INTERFACE_PAR_PTRS_15 0x00000000
  2. Determine the base address for the per-interface parameter table. There is only one EMIF interface in the I/O row, because only one gpt_INTERFACE_PAR_PTRS has a non-zero value.

    The base address for the per-interface parameter table = 0x500_0000 + 0x64 = 0x500_0064.

  3. Read the per-interface parameter table starting from its base address of 0x500_0064. The content of the per-interface parameter table is shown below.
    Address Field Name Value
    Bit [31:24] Bit [23:16] Bit [15:8] Bit [7:0]
    0x500_0064 pt_INTERFACE_PAR_VER pt_IP_VER 0x00024C40
    0x500_0068 pt_UNUSED pt_DEBUG_DATA_PTR 0x000001A0
    0x500_006C pt_RESERVED pt_ CONTROLLER_ TYPE pt_ DIMM_ TYPE pt_ MEMORY_ TYPE 0x00000201
    0x500_0070 pt_AFI_CLK_FREQ_KHZ 0x000411AC
    0x500_0074 pt_ NUM_ RANKS pt_ WRITE_ LATENCY pt_ READ_ LATENCY pt_ BURST_ LEN 0x01121708
    0x500_0078 pt_ NUM_ DQ pt_ NUM_ DQS_RD pt_ NUM_ DQS_WR pt_ NUM_ DIMMS 0x48090901
    0x500_007C pt_CS_WIDTH pt_BANK_ WIDTH pt_ADDR_ WIDTH pt_NUM_DM 0x01021109
    0x500_0080 pt_BANK_ GROUP_ WIDTH pt_C_WIDTH pt_ODT_ WIDTH pt_CKE_ WIDTH 0x02000101
    0x500_0084 pt_NUM_ LRDIMM_CFG pt_CAL_ DATA_SIZE pt_CK_WIDTH pt_ADDR_ MIRROR 0x05140100
    0x500_0088 pt_NUM_ DATA_LANES pt_NUM_ CA_LANES pt_NUM_ CENTERS pt_NUM_AC_ ROM_ENUMS 0x09040434
    0x500_008C pt_ODT_TABLE_LO 0x00000004
    0x500_0090 pt_ODT_TABLE_HI 0x00000000
    0x500_0094 pt_RESERVED 0x0D00C081
    0x500_0098 pt_CAL_DATA_PTR pt_RESERVED 0x00B00000
    0x500_009C pt_DBG_SKIP_RANKS 0x00000000
    0x500_00A0 pt_DBG_SKIP_GROUPS 0x00000000
    0x500_00A4 pt_DBG_SKIP_STEPS 0x00670000
    0x500_00A8 pt_TILE_ID_PTR pt_NUM_DIMM pt_NUM_MR 0x00C4070C
    0x500_00AC pt_MR_PTR pt_PIN_ADDR_PTR 0x017000D8
  4. Determine the base address for debug_data_structure.
    Base address for debug_data_struct = 0x500_0000 + pt_DEBUG_DATA_PTR
                                   = 0x500_0000 + 0x1A0
                                   = 0x500_01A0
  5. Read the debug_data_struct starting from its base address of 0x500_01A0. Below is the content for the debug_data_struct:
    Address Parameter Value
    0x500_01A0 data_size 0x00000000
    0x500_01A4 status 0x00000006
    0x500_01A8 requested_command 0x000003E8
    0x500_01AC command_status 0x00000000
    0x500_01B0 command_parameters[0] 0x00000000
    0x500_01B4 command_parameters[1] 0x00000000
    0x500_01B8 command_parameters[2] 0x00000000
    0x500_01BC command_parameters[3] 0x00000000
    0x500_01C0 mem_summary_report_pointer 0x05000354
    0x500_01C4 mem_cal_report_pointer 0x050003A0
  6. Read the memory_summary_report from the address starting at 0x500_0354.
    • Read from report_flags (address = 0x500_0358). Ensure the LSB of the readdata is 1’b1 (indicating that the calibration report is ready), before reading the other members in the memory_summary_report structure or the mem_cal_report structure.
    • In this example, error_stage, error_group and error_code are all 0, because the calibration is successful.
    Address Parameter Value
    0x5000354 data_size 0x00000013
    0x5000358 report_flags 0x01000001
    0x5000360 error_stage 0x00000000
    0x5000364 error_group 0x00000000
    0x5000368 error_code 0x00000000
    0x500039C in_out_rate 0x00000014
  7. Read the mem_cal_report from the address beginning at 0x500_03A0.
    Address Parameter Value
    0x500_03A0 data_size 0x00000021
    0x500_03A4 debug_cal_data_struct_pointer__cal_data_dq_in 0x05000424
    0x500_03A8 debug_cal_data_struct_pointer__cal_data_dq_out 0x05000544
    0x500_03AC debug_cal_data_struct_pointer__cal_data_dm_dbi_in 0x05000664
    0x500_03B0 debug_cal_data_struct_pointer__cal_data_dm_dbi_out 0x05000688
    0x500_03B4 debug_cal_data_struct_pointer__cal_data_dqs_in 0x050006AC
    0x500_03B8 debug_cal_data_struct_pointer__cal_data_dqs_en 0x050006D0
    0x500_03BC debug_cal_data_struct_pointer__cal_data_dqs_en_b 0x050006F4
    0x500_03C0 debug_cal_data_struct_pointer__cal_data_dqs_out 0x05000718
    0x500_03C4 debug_cal_data_struct_pointer__vrefin 0x0500073C
    0x500_03C8 debug_cal_data_struct_pointer__vrefout 0x05000760
    0x500_03CC debug_cal_data_struct_pointer__cal_data_ca 0x05000784
    0x500_03D4 debug_cal_data_struct_pointer__vfifo* 0x05000878
    0x500_03D8 debug_cal_data_struct_pointer__lfifo* 0x05000884
    0x500_03DC debug_cal_data_struct_pointer__dcc_dq_in* 0x05000890
    0x500_03E0 debug_cal_data_struct_pointer__dcc_dq_out* 0x050008D8
    0x500_03E4 debug_cal_data_struct_pointer__dcc_dm_dbi_in* 0x05000920
    0x500_03E8 debug_cal_data_struct_pointer__dcc_dm_dbi_out* 0x0500092C
    0x500_03EC debug_cal_data_struct_pointer__dcc_dqs_in* 0x05000938
    0x500_03F0 debug_cal_data_struct_pointer__dcc_dqs_out* 0x05000944
    0x500_03F4 debug_cal_data_struct_pointer__dcc_ca* 0x05000950
    0x500_03F8 debug_cal_data_struct_pointer__vrefout_all_ranks* 0x05000984
    0x500_03FC debug_cal_data_struct_pointer__ctle_out* 0x05000990
    0x500_0400 debug_cal_data_struct_pointer__ctle_in_dq* 0x0500099C
    0x500_0404 debug_cal_data_struct_pointer__ctle_in_dqs* 0x050009E4
    0x500_040C write_lat 0x00000005
    0x500_0410 read_lat 0x0000000D
    0x500_0414 rank_skew_data_out 0x00000000
    0x500_0418 rank_skew_dqsen 0x00000000
    0x500_041C extra_rank_delay_any_to_read 0x00000000
    0x500_0420 extra_rank_delay_any_to_write 0x00000000
    Note: * Each address stores the setting for 4 pins or 4 groups.
  8. Read the calibration result for DQ input setting (read path) starting from address 0x0500_0424.
    • The data at address 0x0500_0424 has the calibration result for DQ[0].
    • The data at address 0x0500_0428 has the calibration result for DQ[1].
    • The data at address 0x0500_042C has the calibration result for DQ[2], and so forth.

    For data at each address:

    • Bit[15:0] corresponds to the calibrated setting.
    • Bit[23:16] corresponds to the left edge margin.
    • Bit[31:24] corresponds to the right edge margin.
  9. Repeat step 8 for other pins.
  10. Read the Vrefin setting starting from address 0x0500_073C.
    • The data at address 0x0500_073C has the calibration result for group 0.
    • The data at address 0x0500_0740 has the calibration result for group 1, and so forth.

    For Vrefin/Vrefout calibration setting:

    • Bit[15:8] corresponds to Vref_range:
      • Vref_range =0 means range of 60-92.5% of VCCIO/VREFDQ.
      • Vref_range =1 means range of 45-77.5% of VCCIO/VREFDQ.
    • Bit[7:0] corresponds to Vref_setting where each step is 0.65%.
    For example, in DDR4, VCCIO/VREFDQ is 1.2V. Assuming you obtain 0x122:
    • Vref_range = 0x1
    • Vref_setting =0x22 = 34 (decimal)

    The Vref value in volts = ((34*0.0065) + 0.45) x 1.2V = 0.805V.

  11. Read the mem_summary_report starting from address 0x05000354.
    • The data at 0x5000360 indicates the stage at which calibration first failed. (ENUM_CAL_STAGE).
    • The data at 0x5000364 contains per-group status. Each bit corresponds to a dqs group. If a bit is set 1, then the corresponding group failed in the stage indicated by error_stage.
    • The data at 0x5000368 contains detailed calibration status (ENUM_CAL_ERROR).
  12. For a calibration setting that is stored as 8-bit data (for example, vfifo, lfifo, dcc*, ctle*), each address stores the setting for 4 pins or 4 groups. If you want to read the vfifo setting for this interface implemented in 9 DQS groups, reading the data from address 0x500_0878, 0x500_087C and 0x500_0880 is adequate.
    • Bit [ 7:0] @ address 0x500_0878 = vfifo setting for group 0
    • Bit [15:8] @ address 0x500_0878 = vfifo setting for group 1
    • Bit [23:16] @ address 0x500_0878 = vfifo setting for group 2
    • Bit [31:24] @ address 0x500_0878 = vfifo setting for group 3
    • Bit [ 7:0] @ address 0x500_087C = vfifo setting for group 4
    • Bit [15:8] @ address 0x500_087C = vfifo setting for group 5
    • Bit [23:16] @ address 0x500_087C = vfifo setting for group 6
    • Bit [31:24] @ address 0x500_087C = vfifo setting for group 7
    • Bit [ 7:0] @ address 0x500_0880 = vfifo setting for group 9
  13. All the debug_cal_data is initialized with an all-1 value. Getting an all-1 value for given calibration data (such as dcc-related calibration) means that the value is not overwritten after calibration and you can ignore it.
Level Two Title