External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

Download PDF
ID 683216
Date 1/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP 2. Intel® Agilex™ FPGA EMIF IP – Introduction 3. Intel® Agilex™ FPGA EMIF IP – Product Architecture 4. Intel® Agilex™ FPGA EMIF IP – End-User Signals 5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support 7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support 8. Intel® Agilex™ FPGA EMIF IP – Timing Closure 9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure 10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization 11. Intel® Agilex™ FPGA EMIF IP – Debugging 12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives 13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP x
1.1. Release Information
2. Intel® Agilex™ FPGA EMIF IP – Introduction x
2.1. Intel® Agilex™ EMIF IP Protocol and Feature Support 2.2. Intel® Agilex™ EMIF IP Design Flow 2.3. Intel® Agilex™ EMIF IP Design Checklist
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture x
3.1. Intel® Agilex™ EMIF Architecture: Introduction 3.2. Intel® Agilex™ EMIF Sequencer 3.3. Intel® Agilex™ EMIF Calibration 3.4. Intel® Agilex™ EMIF Controller 3.5. User-requested Reset in Intel® Agilex™ EMIF IP 3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem
3.1. Intel® Agilex™ EMIF Architecture: Introduction x
3.1.1. Intel® Agilex™ EMIF Architecture: I/O Subsystem 3.1.2. Intel® Agilex™ EMIF Architecture: I/O SSM 3.1.3. Intel® Agilex™ EMIF Architecture: I/O Bank 3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane 3.1.5. Intel® Agilex™ EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel® Agilex™ EMIF Architecture: PHY Clock Tree 3.1.7. Intel® Agilex™ EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel® Agilex™ EMIF Architecture: Clock Phase Alignment
3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane x
3.1.4.1. Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme
3.3. Intel® Agilex™ EMIF Calibration x
3.3.1. Intel® Agilex™ Calibration Stages 3.3.2. Intel® Agilex™ Calibration Stages Descriptions 3.3.3. Intel® Agilex™ Calibration Flowchart 3.3.4. Intel® Agilex™ Calibration Algorithms
3.3.4. Intel® Agilex™ Calibration Algorithms x
3.3.4.1. Calibration Algorithms for DDR4 3.3.4.2. Calibration Algorithms for QDR-IV 3.3.4.3. Guidelines for Debugging Calibration Issues
3.3.4.1. Calibration Algorithms for DDR4 x
3.3.4.1.1. DDR4 Read Calibration 3.3.4.1.2. DDR4 Write Calibration
3.3.4.2. Calibration Algorithms for QDR-IV x
3.3.4.2.1. QDR-IV Read Calibration 3.3.4.2.2. QDR-IV Write Calibration
3.3.4.3. Guidelines for Debugging Calibration Issues x
3.3.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 3.3.4.3.2. Debugging Address and Command Leveling Calibration Failure 3.3.4.3.3. Debugging Address and Command Deskew Failure 3.3.4.3.4. Debugging DQS Enable Failure 3.3.4.3.5. Debugging Read Deskew Calibration Failure 3.3.4.3.6. Debugging VREFIN Calibration Failure 3.3.4.3.7. Debugging LFIFO Calibration Failure 3.3.4.3.8. Debugging Write Leveling Failure 3.3.4.3.9. Debugging Write Deskew Calibration Failure 3.3.4.3.10. Debugging VREFOUT Calibration Failure
3.4. Intel® Agilex™ EMIF Controller x
3.4.1. Hard Memory Controller 3.4.2. Intel® Agilex™ Hard Memory Controller Rate Conversion Feature
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features 3.4.1.2. Hard Memory Controller Main Control Path 3.4.1.3. Data Buffer Controller
3.6. Intel® Agilex™ EMIF for Hard Processor Subsystem x
3.6.1. Restrictions on I/O Bank Usage for Intel® Agilex™ EMIF IP with HPS
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals x
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions 4.2. Intel® Agilex™ EMIF IP AFI Signals 4.3. Intel® Agilex™ EMIF IP AFI 4.0 Timing Diagrams 4.4. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables
4.1. Intel® Agilex™ EMIF IP Interface and Signal Descriptions x
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV
4.1.1. Intel Agilex EMIF IP Interfaces for DDR4 x
4.1.1.1. local_reset_req for DDR4 4.1.1.2. local_reset_status for DDR4 4.1.1.3. pll_ref_clk for DDR4 4.1.1.4. pll_locked for DDR4 4.1.1.5. ac_parity_err for DDR4 4.1.1.6. oct for DDR4 4.1.1.7. mem for DDR4 4.1.1.8. status for DDR4 4.1.1.9. afi_reset_n for DDR4 4.1.1.10. afi_clk for DDR4 4.1.1.11. afi_half_clk for DDR4 4.1.1.12. afi for DDR4 4.1.1.13. emif_usr_reset_n for DDR4 4.1.1.14. emif_usr_clk for DDR4 4.1.1.15. ctrl_amm for DDR4 4.1.1.16. ctrl_amm_aux for DDR4 4.1.1.17. ctrl_auto_precharge for DDR4 4.1.1.18. ctrl_user_priority for DDR4 4.1.1.19. ctrl_ecc_user_interrupt for DDR4 4.1.1.20. ctrl_ecc_readdataerror for DDR4 4.1.1.21. ctrl_ecc_status for DDR4 4.1.1.22. ctrl_mmr_slave for DDR4 4.1.1.23. hps_emif for DDR4 4.1.1.24. emif_calbus for DDR4 4.1.1.25. emif_calbus_clk for DDR4
4.1.2. Intel Agilex EMIF IP Interfaces for QDR-IV x
4.1.2.1. local_reset_req for QDR-IV 4.1.2.2. local_reset_status for QDR-IV 4.1.2.3. pll_ref_clk for QDR-IV 4.1.2.4. pll_locked for QDR-IV 4.1.2.5. oct for QDR-IV 4.1.2.6. mem for QDR-IV 4.1.2.7. status for QDR-IV 4.1.2.8. afi_reset_n for QDR-IV 4.1.2.9. afi_clk for QDR-IV 4.1.2.10. afi_half_clk for QDR-IV 4.1.2.11. afi for QDR-IV 4.1.2.12. emif_usr_reset_n for QDR-IV 4.1.2.13. emif_usr_clk for QDR-IV 4.1.2.14. ctrl_amm for QDR-IV 4.1.2.15. emif_calbus for QDR-IV 4.1.2.16. emif_calbus_clk for QDR-IV
4.2. Intel® Agilex™ EMIF IP AFI Signals x
4.2.1. AFI Clock and Reset Signals 4.2.2. AFI Address and Command Signals 4.2.3. AFI Write Data Signals 4.2.4. AFI Read Data Signals 4.2.5. AFI Calibration Status Signals 4.2.6. AFI Tracking Management Signals 4.2.7. AFI Shadow Register Management Signals
4.3. Intel® Agilex™ EMIF IP AFI 4.0 Timing Diagrams x
4.3.1. AFI Address and Command Timing Diagrams 4.3.2. AFI Write Sequence Timing Diagrams 4.3.3. AFI Read Sequence Timing Diagrams 4.3.4. AFI Calibration Status Timing Diagram
4.4. Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables x
4.4.1. ctrlcfg0 4.4.2. ctrlcfg1 4.4.3. dramtiming0 4.4.4. sbcfg1 4.4.5. caltiming0 4.4.6. caltiming1 4.4.7. caltiming2 4.4.8. caltiming3 4.4.9. caltiming4 4.4.10. caltiming9 4.4.11. dramaddrw 4.4.12. sideband0 4.4.13. sideband1 4.4.14. sideband4 4.4.15. sideband6 4.4.16. sideband7 4.4.17. sideband9 4.4.18. sideband11 4.4.19. sideband12 4.4.20. sideband13 4.4.21. sideband14 4.4.22. dramsts 4.4.23. niosreserve0 4.4.24. niosreserve1 4.4.25. sideband16 4.4.26. ecc3: ECC Error and Interrupt Configuration 4.4.27. ecc4: Status and Error Information 4.4.28. ecc5: Address of Most Recent SBE/DBE 4.4.29. ecc6: Address of Most Recent Correction Command Dropped 4.4.30. ecc7: Extension for Address of Most Recent SBE/DBE 4.4.31. ecc8: Extension for Address of Most Recent Correction Command Dropped
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Options 5.2. Simulation Walkthrough
5.2. Simulation Walkthrough x
5.2.1. Calibration Modes 5.2.2. Simulation Scripts 5.2.3. Functional Simulation with Verilog HDL 5.2.4. Functional Simulation with VHDL 5.2.5. Simulating the Design Example
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support x
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 6.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 6.3. Register Map IP-XACT Support for Intel® Agilex™ EMIF DDR4 IP 6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 6.5. DDR4 Board Design Guidelines
6.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
6.1.1. Intel Agilex EMIF IP DDR4 Parameters: General 6.1.2. Intel Agilex EMIF IP DDR4 Parameters: Memory 6.1.3. Intel Agilex EMIF IP DDR4 Parameters: Mem I/O 6.1.4. Intel Agilex EMIF IP DDR4 Parameters: FPGA I/O 6.1.5. Intel Agilex EMIF IP DDR4 Parameters: Mem Timing 6.1.6. Intel Agilex EMIF IP DDR4 Parameters: Controller 6.1.7. Intel Agilex EMIF IP DDR4 Parameters: Diagnostics 6.1.8. Intel Agilex EMIF IP DDR4 Parameters: Example Designs
6.4. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 6.4.2. Intel® Agilex™ FPGA EMIF IP Resources 6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
6.4.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
6.4.1.1. Estimating Pin Requirements 6.4.1.2. DIMM Options 6.4.1.3. Maximum Number of Interfaces
6.4.2. Intel® Agilex™ FPGA EMIF IP Resources x
6.4.2.1. OCT 6.4.2.2. PLL
6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
6.4.3.1. Intel® Agilex™ FPGA EMIF IP Banks 6.4.3.2. General Guidelines 6.4.3.3. x4 DIMM Implementation 6.4.3.4. Specific Pin Connection Requirements 6.4.3.5. Command and Address Signals 6.4.3.6. Clock Signals 6.4.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.5. DDR4 Board Design Guidelines x
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices 6.5.2. Clamshell Topology 6.5.3. General Layout Routing Guidelines 6.5.4. Reference Stackup 6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies 6.5.7. Intel® Agilex™ EMIF Pin Swapping Guidelines
6.5.1. Terminations for DDR4 with Intel® Agilex™ Devices x
6.5.1.1. Dynamic On-Chip Termination (OCT) 6.5.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.5.1.3. Choosing Terminations on Intel® Agilex™ FPGA Devices 6.5.1.4. On-Chip Termination Recommendations for Intel® Agilex™ FPGA Devices
6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.5.5.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, LRDIMM, and SODIMM DDR4 Topologies 6.5.5.2. Two DIMMs per Channel (2DPC) for UDIMM, RDIMM, and LRDIMM DDR4 Topologies 6.5.5.3. Two DIMMs per Channel (2DPC) for SODIMM Topology 6.5.5.4. Skew Matching Guidelines for DIMM Configurations 6.5.5.5. Power Delivery Recommendations for the Memory / DIMM Side
6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.5.6.1. Single Rank x 8 Discrete (Component) Topology 6.5.6.2. Single Rank x 16 Discrete (Component) Topology 6.5.6.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and R Rank x 16 Discrete (Component) Topologies 6.5.6.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.5.6.5. Power Delivery Recommendations for DDR4 Discrete Configurations
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support x
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions 7.2. Intel® Agilex™ External Memory Interfaces Intel® Calibration IP Parameters 7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning 7.4. QDR-IV Board Design Guidelines
7.1. Intel® Agilex™ FPGA EMIF IP Parameter Descriptions x
7.1.1. Intel Agilex EMIF IP QDR-IV Parameters: General 7.1.2. Intel Agilex EMIF IP QDR-IV Parameters: Memory 7.1.3. Intel Agilex EMIF IP QDR-IV Parameters: FPGA I/O 7.1.4. Intel Agilex EMIF IP QDR-IV Parameters: Mem Timing 7.1.5. Intel Agilex EMIF IP QDR-IV Parameters: Controller 7.1.6. Intel Agilex EMIF IP QDR-IV Parameters: Diagnostics 7.1.7. Intel Agilex EMIF IP QDR-IV Parameters: Example Designs
7.3. Intel® Agilex™ FPGA EMIF IP Pin and Resource Planning x
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins 7.3.2. Intel® Agilex™ FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP
7.3.1. Intel® Agilex™ FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. Maximum Number of Interfaces
7.3.2. Intel® Agilex™ FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP x
7.3.3.1. Intel® Agilex™ FPGA EMIF IP Banks 7.3.3.2. General Guidelines 7.3.3.3. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 7.3.3.4. QDR IV SRAM Clock Signals 7.3.3.5. QDR IV SRAM Data, DINV, and QVLD Signals 7.3.3.6. Specific Pin Connection Requirements 7.3.3.7. Resource Sharing Guidelines (Multiple Interfaces)
7.4. QDR-IV Board Design Guidelines x
7.4.1. General Layout Routing Guidelines 7.4.2. Reference Stackup 7.4.3. Routing Guidelines for QDR-IV Topology 7.4.4. Intel® Agilex™ EMIF Design Guideline Summary
7.4.3. Routing Guidelines for QDR-IV Topology x
7.4.3.1. QDR-IV Single Device Memory Topology 7.4.3.2. Skew Matching Guidelines for QDR-IV Configurations 7.4.3.3. Power Delivery Recommendation for QDR-IV Configurations
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure x
8.1. Timing Closure 8.2. Optimizing Timing
8.1. Timing Closure x
8.1.1. Timing Analysis
8.1.1. Timing Analysis x
8.1.1.1. PHY or Core
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure x
9.1. I/O Timing Closure Overview 9.2. Collateral Generated with Your EMIF IP 9.3. SPICE Decks 9.4. File Organization 9.5. Top-level Parameterization File 9.6. IP-Supplied Parameters that You Might Need to Override 9.7. Multi-Rank Topology 9.8. Pin Parasitics 9.9. Mask Evaluation
9.3. SPICE Decks x
9.3.1. Address/Command Simulation Deck 9.3.2. FPGA Write Operation Simulation Deck 9.3.3. FPGA Read Operation Simulation Deck
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Auto-Precharge Commands 10.4.2. Additive Latency 10.4.3. Bank Interleaving 10.4.4. Additive Latency and Bank Interleaving 10.4.5. User-Controlled Refresh 10.4.6. Frequency of Operation 10.4.7. Series of Reads or Writes 10.4.8. Data Reordering 10.4.9. Starvation Control 10.4.10. Command Reordering 10.4.11. Bandwidth 10.4.12. Enable Command Priority Control 10.4.13. Controller Pre-pay and Post-pay Refresh (DDR4 Only)
10.4.1. Auto-Precharge Commands x
10.4.1.1. Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces
11. Intel® Agilex™ FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Hardware Debugging Guidelines 11.6. Categorizing Hardware Issues 11.7. Debugging with the External Memory Interface Debug Toolkit 11.8. Using the Default Traffic Generator 11.9. Using the Configurable Traffic Generator (TG2) 11.10. EMIF On-Chip Debug Port 11.11. Efficiency Monitor
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages 11.2.4. Modifying the Example Driver to Replicate the Failure
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer x
11.4.1. Signals to Monitor with the Signal Tap Logic Analyzer
11.5. Hardware Debugging Guidelines x
11.5.1. Create a Simplified Design that Demonstrates the Same Issue 11.5.2. Measure Power Distribution Network 11.5.3. Measure Signal Integrity and Setup and Hold Margin 11.5.4. Vary Voltage 11.5.5. Operate at a Lower Speed 11.5.6. Determine Whether the Issue Exists in Previous Versions of Software 11.5.7. Determine Whether the Issue Exists in the Current Version of Software 11.5.8. Try A Different PCB 11.5.9. Try Other Configurations 11.5.10. Debugging Checklist
11.6. Categorizing Hardware Issues x
11.6.1. Signal Integrity Issues 11.6.2. Hardware and Calibration Issues
11.6.1. Signal Integrity Issues x
11.6.1.1. Characteristics of Signal Integrity Issues 11.6.1.2. Evaluating Signal Integrity Issues
11.6.1.2. Evaluating Signal Integrity Issues x
11.6.1.2.1. Skew 11.6.1.2.2. Crosstalk 11.6.1.2.3. Power System 11.6.1.2.4. Clock Signals 11.6.1.2.5. Address and Command Signals 11.6.1.2.6. Read Data Valid Window and Eye Diagram 11.6.1.2.7. Write Data Valid Window and Eye Diagram 11.6.1.2.8. OCT and ODT Usage
11.6.2. Hardware and Calibration Issues x
11.6.2.1. Postamble Timing Issues and Margin 11.6.2.2. Intermittent Issue Evaluation
11.7. Debugging with the External Memory Interface Debug Toolkit x
11.7.1. Prerequisites for Using the EMIF Debug Toolkit 11.7.2. Configuring a Design to Use the Toolkit 11.7.3. Launching the EMIF Debug Toolkit 11.7.4. Using the EMIF Debug Toolkit 11.7.5. Exporting Tables 11.7.6. Viewing Reports Graphically in the Eye Viewer
11.7.2. Configuring a Design to Use the Toolkit x
11.7.2.1. Generating a Design Example with the Debug Toolkit 11.7.2.2. Creating a Design Example with Multiple External Memory Interfaces 11.7.2.3. Enabling the EMIF Toolkit in an Existing Design
11.7.4. Using the EMIF Debug Toolkit x
11.7.4.1. Memory Configuration Tab 11.7.4.2. Calibration Tab 11.7.4.3. Guidelines for Debugging Calibration Issues 11.7.4.4. Calibration Report Tab 11.7.4.5. Calibrate Termination Tab 11.7.4.6. Vref Margining Tab 11.7.4.7. Driver Margining Tab 11.7.4.8. ISSPs Tab 11.7.4.9. Pin Delay Settings Tab
11.7.4.2. Calibration Tab x
11.7.4.2.1. Rerunning Calibration 11.7.4.2.2. Rerunning the Traffic Generator
11.7.4.3. Guidelines for Debugging Calibration Issues x
11.7.4.3.1. Debugging Calibration Failure Using Information from the Calibration report 11.7.4.3.2. Debugging Address and Command Leveling Calibration Failure 11.7.4.3.3. Debugging Address and Command Deskew Failure 11.7.4.3.4. Debugging DQS Enable Failure 11.7.4.3.5. Debugging Read Deskew Calibration Failure 11.7.4.3.6. Debugging VREFIN Calibration Failure 11.7.4.3.7. Debugging LFIFO Calibration Failure 11.7.4.3.8. Debugging Write Leveling Failure 11.7.4.3.9. Debugging Write Deskew Calibration Failure 11.7.4.3.10. Debugging VREFOUT Calibration Failure
11.8. Using the Default Traffic Generator x
11.8.1. Reading the Default Traffic Generator Status 11.8.2. Running Infinite Traffic using the Default Traffic Generator 11.8.3. Changing the Reset Trigger of the Default Traffic Generator 11.8.4. Observing Generated Traffic with Signal Tap
11.9. Using the Configurable Traffic Generator (TG2) x
11.9.1. Enabling the Traffic Generator in a Design Example 11.9.2. Traffic Generator Block Description 11.9.3. Default Traffic Pattern 11.9.4. Configuration and Status Registers 11.9.5. User Pattern 11.9.6. Traffic Generator Status 11.9.7. Starting Traffic with the Traffic Generator 11.9.8. Traffic Generator Configuration User Interface
11.9.5. User Pattern x
11.9.5.1. Test Duration / Instruction pattern 11.9.5.2. Address Pattern 11.9.5.3. Data Pattern and Byte Enable
11.9.5.2. Address Pattern x
11.9.5.2.1. Address Generator Modes 11.9.5.2.2. Address Generator MSB Indices 11.9.5.2.3. Address Generator Effective Width 11.9.5.2.4. Address Generator Relative Frequencies 11.9.5.2.5. Address Pattern Examples - Basic Mode 11.9.5.2.6. Address Pattern Examples - Advanced Mode
11.9.8. Traffic Generator Configuration User Interface x
11.9.8.1. Connecting the Traffic Generator 11.9.8.2. Configuring the Traffic Generator 11.9.8.3. Traffic Generator Preset Selection 11.9.8.4. Traffic Generator Status Report 11.9.8.5. Examples of Configuring the TG2 Traffic Generator
11.10. EMIF On-Chip Debug Port x
11.10.1. Enabling the On-Chip Debug Port 11.10.2. I/O SSM calbus Bridge Data Structures and Usage 11.10.3. I/O SSM User-RAM Data Structures and Usage 11.10.4. Debug Interface Structure 11.10.5. Example: Reading Calibration Results and Margins with the On-Chip Debug Port
11.10.3. I/O SSM User-RAM Data Structures and Usage x
11.10.3.1. Parameter Tables 11.10.3.2. Parameter Table Enums
11.10.3.1. Parameter Tables x
11.10.3.1.1. Global Parameter Table 11.10.3.1.2. Per-interface Parameter Table Structure 11.10.3.1.3. Parameter Table Arrays Cal Data Array (pt_CAL_DATA_PTR) MR Array (pt_MR_PTR) Pin Address Array (pt_PIN_ADDR_PTR) Tile ID Array (pt_TILE_ID_PTR)
11.10.4. Debug Interface Structure x
11.10.4.1. Debug Data Structures 11.10.4.2. Debug Enums
11.11. Efficiency Monitor x
11.11.1. Enabling the Efficiency Monitor in a Design Example 11.11.2. Efficiency Monitor Block Descriptions 11.11.3. Control and Status Registers 11.11.4. Opening the Efficiency Monitor Toolkit
1. About the External Memory Interfaces Intel® Agilex™ FPGA IP
2. Intel® Agilex™ FPGA EMIF IP – Introduction
3. Intel® Agilex™ FPGA EMIF IP – Product Architecture
4. Intel® Agilex™ FPGA EMIF IP – End-User Signals
5. Intel® Agilex™ FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ FPGA EMIF IP – DDR4 Support
7. Intel® Agilex™ FPGA EMIF IP – QDR-IV Support
8. Intel® Agilex™ FPGA EMIF IP – Timing Closure
9. Intel® Agilex™ FPGA EMIF IP – I/O Timing Closure
10. Intel® Agilex™ FPGA EMIF IP – Controller Optimization
11. Intel® Agilex™ FPGA EMIF IP – Debugging
12. External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives
13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

11.10.3.1.3. Parameter Table Arrays

This topic describes the structure of some arrays whose addresses are stored in the parameter table. These arrays are used during calibration and may be useful for debugging your design.

Cal Data Array (pt_CAL_DATA_PTR)

The Cal Data Array’s base address is equal to: (user_ram base address) + (offset for cal_data array, read from pt_CAL_DATA_PTR)

Table 176.  cal_data Array
Offset from Pointer Address Entry Size (bytes)
0x0 STARTING_VREFIN 4
0x4 CAL_TREFI 4
0x8 CAL_TRFC 4
0xC CAL_ADDR0 4
0x10 CAL_ADDR1 4

MR Array (pt_MR_PTR)

The MR Array’s base address is equal to: (user_ram base address) + (offset for MR array, read from pt_MR_PTR)

Each array element is 32 bits wide. There can be up to three types of information in this array, as follows:

  • Values to be written into Mode Registers. For ordering refer to ENUM_MR_INDEX. The number of entries of this type is pt_NUM_MR, and should be 0 for non-DDR protocols. Each entry is coded as 32 bits: {19'b0, A[12:0]} (Bank ADDR not included).
  • On RDIMM or LRDIMM, the data above is followed by 64 bit RDIMM configuration, comprising 16 control words of 4 bits each.
  • On LRDIMM, the data above is followed by (pt_NUM_LRDIMM_CFG * 3) number of bytes for extra LRDIMM configuration, each entry being 3 bytes of data with no padding bytes between triplets. Each triplet is defined as {func_sel, address, value}. For example, {3, 2, 6} means F3RC2=6 .

Pin Address Array (pt_PIN_ADDR_PTR)

Each array element is 8 bits wide. The order of the pins is as follows:

  1. All the pins in the appropriate ENUM_AC_ROM_* (based on the protocol used by this design) for command/address pins.
  2. All data pins in the following order, where each item in the brackets below can be a single bit, multi-bit bus (from LSB to MSB), or zero entry (non-existing bus):
    • DDR4: [DQS_T, DQS_C, DM, DQ]
    • QDR-IV: [QKA, QKB, QKA_N, QKB_N, DKA, DKB, DKA_N, DKB_N, DIVA, DIVB, DQA, DQB]

    For example:

    The following table depicts the pin address array for a DDR4 interface of x16 data width, split into two DQS groups:

    Table 177.  Example
    Section Address Element
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr = user_ram base address + pt_PIN_ADDR_PTR DDR4_CKE_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1 DDR4_CKE_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2 DDR4_CKE_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x3 DDR4_CKE_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x4 DDR4_ODT_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x5 DDR4_ODT_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x6 DDR4_ODT_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x7 DDR4_ODT_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x8 DDR4_RESET
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x9 DDR4_ACT
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xA DDR4_CS_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xB DDR4_CS_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xC DDR4_CS_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xD DDR4_CS_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xE DDR4_C_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xF DDR4_C_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x10 DDR4_C_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x11 DDR4_BA_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x12 DDR4_BA_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x13 DDR4_BG_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x14 DDR4_BG_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x15 DDR4_ADD_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x16 DDR4_ADD_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x17 DDR4_ADD_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x18 DDR4_ADD_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x19 DDR4_ADD_4
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1A DDR4_ADD_5
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1B DDR4_ADD_6
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1C DDR4_ADD_7
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1D DDR4_ADD_8
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1E DDR4_ADD_9
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1F DDR4_ADD_10
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x20 DDR4_ADD_11
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x21 DDR4_ADD_12
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x22 DDR4_ADD_13
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x23 DDR4_ADD_14
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x24 DDR4_ADD_15
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x25 DDR4_ADD_16
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x26 DDR4_ADD_17
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x27 DDR4_ADD_18
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x28 DDR4_ADD_19
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x29 DDR4_PAR_IN
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2A REAL_AC_PIN_DDR4_NUM
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2A DDR4_RDATA_EN
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2B DDR4_MRNK_RD
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2C DDR4_WDATA_VALID
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2D DDR4_MRNK_WRT
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2E AC_DDR4_NUM
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2A DDR4_ALERT0_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2B DDR4_ALERT1_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2C DDR4_CK0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2D DDR4_CK0_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2E DDR4_CK1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2F DDR4_CK1_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x30 DDR4_CK2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x31 DDR4_CK2_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x32 DDR4_CK3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x33 DDR4_CK3_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x34 AC_PIN_DDR4_NUM
    2 (DQS_T) Pin Address Array Base Addr + 0x35 DQS_0
    2 (DQS_T) Pin Address Array Base Addr + 0x36 DQS_1
    2 (DQS_C) Pin Address Array Base Addr + 0x37 DQS_N_0
    2 (DQS_C) Pin Address Array Base Addr + 0x38 DQS_N_1
    2 (DM) Pin Address Array Base Addr + 0x39 DM_0
    2 (DM) Pin Address Array Base Addr + 0x40 DM_1
    2 (DQ) Pin Address Array Base Addr + 0x41 DQ_0
    2 (DQ) Pin Address Array Base Addr + 0x42 DQ_1
    2 (DQ) Pin Address Array Base Addr + 0x43 DQ_2
    2 (DQ) Pin Address Array Base Addr + 0x44 DQ_3
    2 (DQ) Pin Address Array Base Addr + 0x45 DQ_4
    2 (DQ) Pin Address Array Base Addr + 0x46 DQ_5
    2 (DQ) Pin Address Array Base Addr + 0x47 DQ_6
    2 (DQ) Pin Address Array Base Addr + 0x48 DQ_7
    2 (DQ) Pin Address Array Base Addr + 0x49 DQ_8
    2 (DQ) Pin Address Array Base Addr + 0x50 DQ_9
    2 (DQ) Pin Address Array Base Addr + 0x51 DQ_10
    2 (DQ) Pin Address Array Base Addr + 0x52 DQ_11
    2 (DQ) Pin Address Array Base Addr + 0x53 DQ_12
    2 (DQ) Pin Address Array Base Addr + 0x54 DQ_13
    2 (DQ) Pin Address Array Base Addr + 0x55 DQ_14
    2 (DQ) Pin Address Array Base Addr + 0x56 DQ_15

    In most cases, each entry is encoded as 8 bits: {lane-index[3:0], pin-index[3:0]}, where lane-index is the index to the lane addresses in pt_TILE_ID_PTR and pin-index is the physical pin index in that lane.

    16-bit encoding is used when the number of data groups exceeds 16, so 4 bits are insufficient. 16-bit encoding is also used for CA pins such as alert_n, which are not necessarily physically located in a CA lane. If an alert_n pin is placed in a data lane, the absolute tile-id value is used: {1'b0, data-lane-index[6:0], pin-index[3:0], 4'b1111}, where data-lane-index is similar to lane-index in 8-bit encoding, except that it is always based off data lanes, regardless of pin types. For 16-bit code, the LSB byte appears first, followed by the MSB byte.

    The lane-index is based off of the corresponding group, specifically either the CA lanes or the data lanes. (For an explanation of CA lanes and data lanes, refer to the comments of pt_TILE_ID_PTR, above).

    For example:

    In a DDR4 interface, the array element for DQ_0 = 8’b0001_0010

    lane_index = 4’b0001

    pin_index = 4’b0010

    Because this is a data pin, you should refer to index 1 in DATA_LANES (that is, “DATA_LANES: TILE ID 1” in Tile ID Array ) to get the actual tile and lane location for DQ0 data pin for this interface.

    The unused slots (such as CKE_3 when there are only 2 CKE pins in the design) must be filled with 8'b0.

Tile ID Array (pt_TILE_ID_PTR)

Each array element is an 8-bit-wide tile-id: {tile-pos[4:0], lane-id[2:0]}. This array contains tile IDs of three groups, in the following order:

  1. Centers.
  2. CA lanes.
  3. Data lanes.

pt_NUM_CENTERS, pt_NUM_CA_LANES, and pt_NUM_DATA_LANES indicate how many tile IDs exist in Centers, CA lanes, and Data lanes respectively.

The table below depicts the Tile ID Array for an example with the following characteristics:

  • pt_NUM_CENTERS = 0x03
  • pt_NUM_CA_LANES = 0x03
  • pt_NUM_DATA_LANES = 0x09
Table 178.  Tile ID Array Example
Address Group Element
Base Address for Tile ID Array = user-ram base address + pt_TILE_ID_PTR offset CENTERS CENTERS: Tile ID 0
Base Address for Tile ID Array + 0x1 CENTERS CENTERS: Tile ID 1
Base Address for Tile ID Array + 0x2 CENTERS CENTERS: Tile ID 2
Base Address for Tile ID Array + 0x3 CA_LANES CA_LANES: Tile ID 0
Base Address for Tile ID Array + 0x4 CA_LANES CA_LANES: Tile ID 1
Base Address for Tile ID Array + 0x5 CA_LANES CA_LANES: Tile ID 2
Base Address for Tile ID Array + 0x6 DATA_LANES DATA_LANES: TILE ID 0
Base Address for Tile ID Array + 0x7 DATA_LANES DATA_LANES: TILE ID 1
Base Address for Tile ID Array + 0x8 DATA_LANES DATA_LANES: TILE ID 2
Base Address for Tile ID Array + 0x9 DATA_LANES DATA_LANES: TILE ID 3
Base Address for Tile ID Array + 0xA DATA_LANES DATA_LANES: TILE ID 4
Base Address for Tile ID Array + 0xB DATA_LANES DATA_LANES: TILE ID 5
Base Address for Tile ID Array + 0xC DATA_LANES DATA_LANES: TILE ID 6
Base Address for Tile ID Array + 0xD DATA_LANES DATA_LANES: TILE ID 7
Base Address for Tile ID Array + 0xE DATA_LANES DATA_LANES: TILE ID 8

The order of lanes inside each group is arbitrary, except that the first address must be the center address with an active sequencer.

Level Two Title