SDI II Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683209
Date 12/09/2022
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
1.6. SDI II Intel® FPGA Design Example Parameters x
1.6.1. Design Example Presets
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

2.9. Upgrading Your Design

When you upgrade your designs to a later version, you may have to add, remove, or edit some of the generated files.

Upgrading from Previous Versions of the Intel® Quartus® Prime Pro Edition Software

  1. Click IP Upgrade to upgrade all the IP and Platform Designer files.
  2. If you have triple-rate or multi-rate designs, update all the Native PHY config files location to the latest version in the simulation run script. For example, in the mentor.do file, update the version as in the following line:
    vlog -sv \$USER_DEFINED_VERILOG_COMPILE_OPTIONS  "\$QSYS_SIMDIR/../rtl/du/sdi_rx_phy/altera_xcvr_native_a10_<version>/
sim/reconfig/altera_xcvr_native_a10_reconfig_parameters_CFG0.sv"
    Note: You should be able to find the updated Native PHY library path in the specified folder indicated in the line.
  3. Generate the same design example configuration in the new Intel® Quartus® Prime release version.
  4. Compare the whole design example directory; replace the files that have changes with the new files and copy over the new files to your existing design.

Upgrading from Intel® Quartus® Prime Standard Edition to Intel® Quartus® Prime Pro Edition

  1. Click IP Upgrade to upgrade all the IP files.
  2. Manually update the Platform Designer system files from the Platform Designer.
  3. Refresh all the Native PHY profiles in the triple-rate or multi-rate RX Native PHY transceiver.
    • Open the sdi_rx_phy.qsys and sdi_rx_sys.qsys or sdi_du_sys.qsys file.
    • At the Selected reconfiguration profile parameter, select 0, and click Refresh selected profile. Refer to notes (1) and (2) in the diagram below.
    • Repeat the previous step for the rest of the profiles accordingly.
    • After you have refreshed all the profiles, switch back to profile 0 and click Generate HDL.
  4. If you have multi-rate or triple-rate designs, update all the Native PHY config files location to the latest version in the simulation run script. For example, in the mentor.do file, update the version as in the following line:
    vlog -sv \$USER_DEFINED_VERILOG_COMPILE_OPTIONS  "\$QSYS_SIMDIR/../rtl/du/sdi_rx_phy/altera_xcvr_native_a10_<version>/
sim/reconfig/altera_xcvr_native_a10_reconfig_parameters_CFG0.sv"
    Note: You should be able to find the updated Native PHY library path in the specified folder indicated in the line.
  5. Generate the same design example configuration in the new Intel® Quartus® Prime Pro Edition release version.
  6. Compare the whole design example directory; replace the files that have changes with the new files and copy over the new files to your existing design.
  7. Update the project QSF file to remove the library switches and modify the SDC_FILE assignment to SDC_ENTITY_FILE assignment for some .sdc files.
    • Remove the following Intel® Quartus® Prime Standard Edition assignments:
      Set_global_assignment -name VERILOG_FILE ../rtl/loopback/fifo/sdi_ii_ed_loopback.v 
-library sdi_du_sys_sdi_ii_rx_phy_mgmt_180

      Set_global_assignment -name SDC_FILE ../rtl/loopback/fifo/sdi_ii_ed_loopback.sdc

      Set_global_assignment -name VERILOG_FILE ../rtl/du/du_top.v 
-library sdi_du_sys_sdi_ii_rx_phy_mgmt_180
    • Add the following Intel® Quartus® Prime Pro Edition assignments:
      Set_global_assignment -name VERILOG_FILE ../rtl/loopback/fifo/sdi_ii_ed_loopback.v

      Set_global_assignment -name SDC_ENTITY_FILE ../rtl/loopback/fifo/sdi_ii_ed_loopback.sdc 
-entity sdi_ii_ed_loopback

      Set_global_assignment -name VERILOG_FILE ../rtl/du/du_top.v
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