SDI II Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683209
Date 12/09/2022
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
1.6. SDI II Intel® FPGA Design Example Parameters x
1.6.1. Design Example Presets
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

1.5. Compiling and Testing the Design

To compile and run a demonstration test on the hardware design example, follow these steps:
  1. Ensure that the hardware design example generation is complete.
  2. Open quartus/sdi_ii_a10_demo.qpf.
  3. Click Processing > Start Compilation.
  4. If you set the Rx core clock (rx_coreclk) Frequency parameter to 297.0/296.70 MHz, set the frequency for CLK1 in the Si5338 (U14) tab of the Clock Control GUI to 297 MHz.
  5. If you enable the Dynamic Tx clock switching feature in the Design Example parameter editor, set the frequency for CLK2 or CLK3 in the Si5338 (U14) tab of the Clock Control GUI.
    • For HD/3G-SDI single-rate and triple-rate designs, set CLK3 to 148.3516 MHz.
    • For multi-rate designs, set CLK2 to 296.7033 MHz.
  6. After successful compilation, the Intel® Quartus® Prime software generates a .sof file in your specified directory.
  7. Configure the selected Intel® Arria® 10 device on the development board using the generated .sof file (Tools > Programmer ).
  8. For serial loopback designs, open the System Console to control the internal video pattern generator. Click Tools > System Debugging Tools > System Console.
    Note: Close the Clock Control GUI and the Programmer window before you open the System Console.
  9. After the initialization, type source ../hwtest/tpg_ctrl.tcl in the System Console to open the pattern generator control user interface. Select your desired video format.

Section Content
Connection and Settings Guidelines
Design Considerations

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