2.5. Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
On-board Oscillator Signals | |||
clk_fpga_b2_p | Input |
1 |
100 MHz clock for reconfiguration Avalon-MM interfaces. |
pcie_ob_refclk_p | Input |
1 |
100 MHz dedicated transceiver reference clock. |
refclk_dp_p | Input |
1 |
270 MHz dedicated transceiver reference clock. |
refclk_sdi_p | Input |
1 |
148.5 or 148.35 MHz dedicated transceiver reference clock. |
refclk_sma_p | Input | 1 |
302 MHz dedicated transceiver reference clock. Programmable to 148.3516 MHz from the Clock Control GUI. |
refclk_fmca_p | Input | 625 MHz dedicated transceiver reference clock. Programmable to 297.0/296.7 MHz from the Clock Control GUI. | |
refclk_fmcb_p | Input | 1 |
625 MHz dedicated transceiver reference clock. Programmable to 296.7033 MHz from the Clock Control GUI. |
User Push Buttons and LEDs | |||
user_pb0 | Input |
1 |
Push button to power down LMK03328 after switching the jumper settings. |
cpu_resetn | Input |
1 |
Global reset. |
user_led_g | Output |
8 |
Green LED display. |
user_led_r | Output |
8 |
Red LED display. |
On-board Si516, SDI Cable Driver and Equalizer Related Pins | |||
sdi_rx_p | Input |
1 |
On-board SDI RX serial data. |
sdi_tx_p | Output |
1 |
On-board SDI TX serial data. |
sdi_clk148_up | Output |
1 |
Voltage control for Si516. |
sdi_clk148_down | Output |
1 |
Voltage control for Si516. |
sdi_mf0_bypass | Output |
1 |
On-board SDI RX Equalizer Bypass. |
sdi_mf1_auto_sleep | Output |
1 |
On-board SDI RX Equalizer Auto Sleep. |
sdi_mf1_mute | Output |
1 |
On-board SDI RX Equalizer Mute. |
sdi_tx_sd_hdn | Output |
1 |
On-board SDI TX cable driver slew rate control. |
Nextera SDI FMC Daughter Card Pins on FMC Port B | |||
fmcb_gbtclk_m2c_p0 | Input |
1 |
297 or 296.7 MHz dedicated transceiver reference clock from FMC port B. |
fmcb_dp_m2c_p2 | Input |
1 |
SDI RX serial data from FMC port B. |
fmcb_la_tx_p1 | Input |
1 |
RX cable equalizer lock status on Nextera daughter card. |
fmcb_dp_c2m_p0 | Output |
1 |
SDI TX serial data from FMC port B. |
fmcb_la_tx_p12 | Output |
1 |
Initialize LMH1983 on Nextera daughter card. |
fmcb_la_tx_n12 | Output |
1 |
F sync signal LMH1983 on Nextera daughter card. |
fmcb_la_tx_p14 | Output |
1 |
V sync signal LMH1983 on Nextera daughter card. |
fmcb_la_tx_n14 | Output | 1 | H sync signal LMH1983 on Nextera daughter card. |
fmcb_la_tx_p15 | Output | 1 | Power-down signal LMH1983 on Nextera daughter card. |
Signal | Direction | Width | Description |
---|---|---|---|
Clocks | |||
rx_cdr_refclk | Input |
1 |
RX transceiver reference clock. This clock must be a free-running clock. |
rx_core_refclk | Input |
1 |
SDI RX core clock. This clock must be a free-running clock. |
tx_pll_refclk | Input |
1 |
TX PLL reference clock. This clock must be a free-running clock. |
tx_pll_refclk_alt | Input |
1 |
Secondary TX PLL reference clock. This clock must be a free-running clock. |
rx_rcfg_mgmt_clk | Input |
1 |
RX reconfiguration management clock, Avalon-MM interface clock, and PHY reset control input clock. This clock must be a free-running clock. |
tx_rcfg_mgmt_clk | Input |
1 |
TX reconfiguration management clock, and Avalon-MM interface clock, and PHY reset control input clock. This clock must be a free-running clock. |
rx_vid_clkout | Output |
1 |
RX transceiver recovered parallel clock for video data. |
tx_vid_clkout | Output |
1 |
TX transceiver recovered parallel clock for video data. |
Reset | |||
tx_resetn | Input |
1 |
TX core and PHY reset signal. |
rx_resetn | Input |
1 |
RX core and PHY reset signal. |
tx_rcfg_mgmt_resetn | Input |
1 | TX reconfiguration reset signal. |
rx_rcfg_mgmt_resetn | Input |
1 |
RX reconfiguration reset signal. |
sdi_rx_rst_proto_out | Output |
1 | Reset signal generated to reset the receiver downstream protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain. |
Video Signal Interfaces (Interface with Video Image and Processing (VIP) Components) | |||
rx_vid_data | Output |
20*N |
Receiver parallel video data out.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
rx_vid_datavalid | Output |
1 |
Data valid signal generated from SDI RX core. The timing must be synchronous to rx_vid_clkout and has the following settings:
|
rx_vid_std | Output |
3 |
Received video standard.
|
rx_vid_locked | Output |
1 |
Frame locked indicates that the IP core has spotted multiple frames with the same timing. |
rx_vid_hsync | Output |
N |
Horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
rx_vid_vsync | Output |
N |
Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
rx_vid_f | Output |
N |
Field bit timing signal. This signal indicates which video field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
rx_vid_trs | Output |
N |
On-board SDI TX cable driver slew rate control.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
tx_vid_data | Output |
20*N |
Receiver output signal that indicates current word is timing reference signal (TRS). This signal asserts at the first word of 3FF 000 000 TRS.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
tx_vid_datavalid | Input |
1 |
Transmitter parallel data valid. The timing (H: High, L: Low) must be synchronous to tx_pclk clock domain and has the following settings:
|
tx_vid_std | Input |
3 |
Indicates the desired transmit video standard.
|
tx_vid_trs | Input |
1 |
Transmitter TRS input. For use in LN, CRC, or payload ID insertion. Assert on the first word of both end of active video (EAV) TRS and start of active video (SAV) TRS. |
Other SDI Video Protocol Interfaces | |||
sdi_tx_enable_crc | Input |
1 |
Enable CRC insertion for all SDI video standards, except SD-SDI. |
sdi_tx_enable_ln | Input |
1 |
Enable LN insertion for all SDI video standards, except SD-SDI. |
sdi_tx_ln | Input |
11*N |
LN insertion in the data stream when sdi_tx_enable_ln = 1.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_tx_ln_b | Input |
11*N |
LN insertion in the data stream when sdi_tx_enable_ln = 1.
Only for 3G level B and, 6G/12G 10-bit Multiplex Type 2.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_tx_vpid_overwrite | Input |
1 |
Enable this signal to overwrite the existing payload ID embedded in the data stream. |
sdi_tx_line_f0 | Input |
11*N |
Indicates the line number to be inserted with the payload ID. |
sdi_tx_line_f1 | Input |
11*N |
|
sdi_tx_vpid_byte1 | Input |
8*N |
Payload ID byte to be inserted in the payload ID field. |
sdi_tx_vpid_byte2 | Input |
8*N |
|
sdi_tx_vpid_byte3 | Input |
8*N |
|
sdi_tx_vpid_byte4 | Input |
8*N |
|
sdi_tx_vpid_byte1_b | Input |
8*N |
|
sdi_tx_vpid_byte2_b | Input |
8*N |
|
sdi_tx_vpid_byte3_b | Input |
8*N |
|
sdi_tx_vpid_byte4_b | Input |
8*N |
|
sdi_rx_coreclk_is_ntsc_paln | Input |
1 |
To indicate whether rx_coreclk is 148.5 MHz or 148.35 MHz:
|
sdi_tx_datavalid | Output |
1 |
Data valid signal generated from SDI TX core. The timing (H: High, L: Low) is synchronous to tx_vid_clkout and has the following settings:
|
sdi_rx_align_locked | Output |
1 |
Alignment locked indicating the IP core has spotted a TRS and word alignment performed. |
sdi_rx_trs_locked | Output |
N |
TRS locked indicating the IP core has spotted six consecutive TRS with same timing.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_rx_clkout_is_ntsc_paln | Output |
1 |
Indicates that the receiver is receiving video rate at integer or fractional frame rate:
|
sdi_rx_format | Output |
4*N |
Received video transport format. Refer to the SDI II IP User Guide for the encoding value.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_rx_ap | Output |
N |
Active picture interval timing signal. This signal asserts when the active picture interval is active. |
sdi_rx_eav | Output |
N |
Receiver output signal that indicates current TRS is EAV. This signal is asserted at the fourth word of TRS, which is the XYZ word. |
sdi_rx_ln | Output |
11*N |
Received line number from protocol. |
sdi_rx_ln_b | Output |
11*N |
|
sdi_rx_crc_error_c | Output |
N |
CRC error status signal from protocol. |
sdi_rx_crc_error_y | Output |
N |
|
sdi_rx_crc_error_c_b | Output |
N |
|
sdi_rx_crc_error_y_b | Output |
N |
|
sdi_rx_line_f0 | Output |
11*N |
Payload ID status from protocol. |
sdi_rx_line_f1 | Output |
11*N |
|
sdi_rx_vpid_byte1 | Output |
8*N |
|
sdi_rx_vpid_byte2 | Output |
8*N |
|
sdi_rx_vpid_byte3 | Output |
8*N |
|
sdi_rx_vpid_byte4 | Output |
8*N |
|
sdi_rx_vpid_checksum_error | Output |
N |
|
sdi_rx_vpid_valid | Output |
N |
|
sdi_rx_vpid_byte1_b | Output |
8*N |
|
sdi_rx_vpid_byte2_b | Output |
8*N |
|
sdi_rx_vpid_byte3_b | Output |
8*N |
|
sdi_rx_vpid_byte4_b | Output |
8*N |
|
sdi_rx_vpid_checksum_error_b | Output |
N |
|
sdi_rx_vpid_valid_b | Output |
N |
|
Transceiver Interfaces | |||
tx_pll_refclk_sel | Input |
1 |
Indicate which of pll_locked signals to be monitored for TX PHY reset controller's reset sequencing. Always set to 1'b0 if you are not doing any TX clock dynamic switching. |
tx_rcfg_cal_busy | Input |
1 |
Transceiver calibration status to TX PHY reset controller. |
rx_rcfg_cal_busy | Input |
1 |
Transceiver calibration status to RX PHY reset controller and Rx reconfiguration management module. |
gxb_rx_serial_data | Input |
1 |
RX transceiver serial data. |
gxb_tx_serial_data | Output |
1 |
TX transceiver serial data. |
gxb_rx_ready | Output |
1 |
RX transceiver status. |
gxb_tx_ready | Output |
1 |
TX transceiver status. |
gxb_rx_cal_busy | Output |
1 |
Calibration status signal from RX transceiver. |
gxb_tx_cal_busy | Output |
1 |
Calibration status signal from TX transceiver. |
tx_pll_locked | Output |
1 |
TX PLL lock status. |
tx_pll_locked_alt | Output |
1 |
TX PLL alt lock status. |
cdr_reconfig_busy | Output |
1 |
RX CDR reconfiguration status. |
tx_reconfig_busy | Output |
1 |
TX PLL/transceiver reconfiguration status. |
Transceiver Reconfiguration Interfaces | |||
gxb_du_rcfg_write | Input |
1 |
Reconfiguration interface signals from transceiver arbiter to duplex mode transceiver. |
gxb_du_rcfg_read | Input |
1 |
|
gxb_du_rcfg_address | Input |
10 |
|
gxb_du_rcfg_writedata | Input |
32 |
|
gxb_du_rcfg_readdata | Output |
32 |
|
gxb_du_rcfg_waitrequest | Output |
1 |
|
gxb_rx_rcfg_write | Input |
1 |
Reconfiguration interface signals from transceiver arbiter to RX transceiver. |
gxb_rx_rcfg_read | Input |
1 |
|
gxb_rx_rcfg_address | Input |
10 |
|
gxb_rx_rcfg_writedata | Input |
32 |
|
gxb_rx_rcfg_readdata | Output |
32 |
|
gxb_rx_rcfg_waitrequest | Output |
1 |
|
gxb_tx_rcfg_write | Input |
1 |
Reconfiguration interface signals from transceiver arbiter to TX transceiver. |
gxb_tx_rcfg_read | Input |
1 |
|
gxb_tx_rcfg_address | Input |
10 |
|
gxb_tx_rcfg_writedata | Input |
32 |
|
gxb_tx_rcfg_readdata | Output |
32 |
|
gxb_tx_rcfg_waitrequest | Output |
1 |
|
rx_rcfg_readdata | Input |
32 |
Reconfiguration interface signals from RX reconfiguration management module to transceiver arbiter. |
rx_rcfg_waitrequest | Input |
1 |
|
rx_rcfg_write | Output |
1 |
|
rx_rcfg_read | Output |
1 |
|
rx_rcfg_address | Output |
10 |
|
rx_rcfg_writedata | Output |
32 |
|
tx_rcfg_readdata | Input |
32 |
Reconfiguration interface signals from TX reconfiguration management module to transceiver arbiter |
tx_rcfg_waitrequest | Input |
1 |
|
tx_rcfg_write | Output |
1 |
|
tx_rcfg_read | Output |
1 |
|
tx_rcfg_address | Output |
10 |
|
tx_rcfg_writedata | Output |
32 |
|
tx_fpll_rcfg_write | Input |
1 |
Reconfiguration interface signals to fPLL Avalon-MM interface. |
tx_fpll_rcfg_read | Input |
1 |
|
tx_fpll_rcfg_writedata | Input |
32 |
|
tx_fpll_rcfg_address | Input |
10 |
|
tx_fpll_rcfg_readdata | Output |
32 |
|
tx_fpll_rcfg_waitrequest | Output |
1 |
Signal | Direction | Width | Description |
---|---|---|---|
Clocks | |||
sdi_tx_clkout | Input |
1 |
TX transceiver recovered parallel clock for video data. |
sdi_rx_clkout | Input |
1 |
RX transceiver recovered parallel clock for video data. |
sdi_reclk_sysclk | Input |
1 |
Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk. |
Resets | |||
sdi_rx_rst_proto | Input |
1 |
Reset signal from SDI RX core to indicate that the protocol is currently held in reset. |
sdi_reclk_rst | Input |
1 |
Reset signal to reclock module (without external VCXO solution). |
SDI Related Signals | |||
sdi_rx_dataout | Input |
20*N |
Receiver recovered parallel video data.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_rx_dataout_valid | Input |
1 |
Data valid signal generated from SDI RX core. |
sdi_rx_std | Input |
3 |
Received video standard from SDI RX core. |
sdi_rx_trs | Input |
N |
Receiver output signal from SDI II IP core that indicates current word is TRS.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_rx_trs_locked | Input |
N |
TRS locked status signal from SDI RX core.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_rx_frame_locked | Input |
1 |
Frame locked status signal from SDI RX core. |
sdi_tx_dataout_valid | Input |
1 |
Data valid signal generated from SDI TX core. |
sdi_rx_h | Input |
1 |
Horizontal blanking interval timing signal extracted from SDI RX core. |
sdi_rx_format | Input |
4 |
Received video transport format. |
sdi_rx_clkout_is_ntsc_paln | Input |
1 |
Indication from SDI RX core that the receiver is receiving video rate at integer or fractional frame rate. |
sdi_tx_datain | Output |
20*N |
Parallel video data input to SDI TX core.
Note: N = 4 (multi-rate design) or 1 (triple-rate design)
|
sdi_tx_datain_valid | Output |
1 |
Data valid for the transmitter parallel data to SDI TX core. |
sdi_tx_trs | Output |
1 |
Transmitter TRS input to indicate that the current word is a TRS to SDI TX core. |
sdi_tx_std | Output |
3 |
Indicates the desired transmit video standard to SDI TX core. |
Voltage Control Signals for On-board Si516 | |||
vcoclk_up | Output |
1 |
Voltage up signal to Si516 to increase the voltage. |
vcoclk_down | Output |
1 |
Voltage down signal to Si516 to decrease the voltage. |
fPLL Reconfiguration Signals | |||
pll_locked | Input |
1 |
PLL lock status signal. |
pll_reconfig_readdata | Input |
32 |
Reconfiguration interface signals to fPLL Avalon-MM interface. |
pll_reconfig_waitrequest | Input |
1 |
|
pll_reconfig_write | Output |
1 |
|
pll_reconfig_read | Output |
1 |
|
pll_reconfig_writedata | Output |
32 | |
pll_reconfig_address | Output |
10 |
Signal | Direction | Width | Description |
---|---|---|---|
On-board Oscillator Signals | |||
clk | Input |
1 |
Reconfiguration clock. This clock should be sharing the same clock as reconfiguration management blocks. |
reset | Input |
1 |
Reset signal. This reset should be sharing the same reset as reconfiguration management blocks. |
rx_rcfg_en | Input |
1 |
RX reconfiguration enable signal. |
tx_rcfg_en | Input |
1 |
TX reconfiguration enable signal. |
rx_rcfg_ch | Input |
2 |
Indicates which channel to be reconfigured on RX. Always assign to 2'b00 for SDI case. |
tx_rcfg_ch | Input |
2 |
Indicates which channel to be reconfigured on TX. Always assign to 2'b00 for SDI case. |
rx_reconfig_mgmt_write | Input |
1 |
Reconfiguration Avalon-MM interfaces from RX reconfiguration management. |
rx_reconfig_mgmt_read | Input |
1 |
|
rx_reconfig_mgmt_address | Input |
10 |
|
rx_reconfig_mgmt_writedata | Input |
32 |
|
rx_reconfig_mgmt_readdata | Output |
32 |
|
rx_reconfig_mgmt_waitrequest | Output |
1 |
|
tx_reconfig_mgmt_write | Input |
1 |
Reconfiguration Avalon-MM interfaces from TX reconfiguration management. |
tx_reconfig_mgmt_read | Input |
1 |
|
tx_reconfig_mgmt_address | Input |
10 |
|
tx_reconfig_mgmt_writedata | Input |
32 |
|
tx_reconfig_mgmt_readdata | Output |
32 |
|
tx_reconfig_mgmt_waitrequest | Output |
1 |
|
reconfig_write | Output |
1 |
Reconfiguration Avalon-MM interfaces to transceiver. |
reconfig_read | Output |
1 |
|
reconfig_address | Output |
10 |
|
reconfig_writedata | Output |
32 |
|
rx_reconfig_readdata | Input |
32 |
|
rx_reconfig_waitrequest | Input |
1 |
|
tx_reconfig_readdata | Input | 1 |
|
tx_reconfig_waitrequest | Input |
1 |
|
rx_cal_busy | Input |
1 |
Calibration status signal from RX transceiver. |
tx_cal_busy | Input |
1 |
Calibration status signal from TX transceiver. |
rx_reconfig_cal_busy | Output |
1 |
Calibration status signal to RX transceiver PHY reset control. |
tx_reconfig_cal_busy | Output |
1 |
Calibration status signal from TX transceiver PHY reset control. |
Video Pattern Generator Signals | |||
clk | Input |
1 |
Clock signal. This clock must be connected to the tx_vid_clkout input signal on TX/Du top. |
rst | Input |
1 |
Reset signal. This reset signal should be synchronized with the tx_vid_clkout clock signal from the TX/Du top. |
bar_100_75n | Input |
1 |
Enable this signal to generate 100% color-bar pattern. Disable to generate 75% color-bar pattern. |
enable | Input |
1 |
This signal acts as a data valid signal to this module. This signal should be connected to the sdi_tx_datavalid signal from the TX/Du top. |
patho | Input |
1 |
Enable this signal to generate pathological pattern. |
blank | Input |
1 |
Enable this signal to generate blank signal. |
no_color | Input |
1 |
Enable this signal to generate bar with no color. |
sgmt_frame | Input |
1 |
Enable this signal to generate payload ID for segmented frame video format when generating 1080i50 or 1080i60 video. |
tx_std | Input |
3 |
Indicates the desired transmit video standard. This input signal must match tx_vid_std on the TX/Du top. |
tx_format | Input |
4 |
Indicates the desired transmit video format. |
dl_mapping | Input |
1 |
Enable this signal to generate data streams with dual-link mapping.
Note: Applicable only for HD dual link or 3G Level B dual link video standard.
|
ntsc_paln | Input |
1 |
Enable this signal to generate payload ID for fractional frame rate video format. Disable to generate integer frame rate video format. |
dout | Output |
20*S |
Data output signal to be connected to the tx_vid_data input signal on the TX/Du top. |
dout_valid | Output |
1 |
Data valid output signal to be connected to the tx_vid_datavalid input signal on the TX/Du top. |
trs | Output |
1 |
TRS output signal to be connected to the tx_vid_trs input signal on the TX/Du top. |
ln | Output |
11*S |
Line number output signal to be connected to the sdi_tx_ln input signal on the TX/Du top. |
dout_b | Output |
20*S |
Data output signal for link B (HD dual link). |
dout_valid_b | Output |
1 |
Data valid output signal for link B (HD dual link). |
trs_b | Output |
1 |
TRS output signal for link B (HD dual link). |
ln_b | Output |
11*S |
Line number output signal to be connected to the sdi_tx_ln_b input signal on the TX/Du top. |
vpid_byte1 | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte1 input signal on TX/Du top. |
vpid_byte2 | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte2 input signal on TX/Du top. |
vpid_byte3 | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte3 input signal on TX/Du top. |
vpid_byte4 | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte4 input signal on TX/Du top. |
vpid_byte1_b | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte1_b input signal on TX/Du top. |
vpid_byte2_b | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte2_b input signal on TX/Du top. |
vpid_byte3_b | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte3_b input signal on TX/Du top. |
vpid_byte4_b | Input |
8*N |
The payload ID output signal to be connected to sdi_tx_vpid_byte4_b input signal on TX/Du top. |
line_f0 | Output |
11*N |
The line number output signal to be inserted with the payload ID. This signal must connect to sdi_tx_line_f0 input signal on TX/Du top. |
line_f1 | Output |
11*N |
The line number output signal to be inserted with the payload ID. This signal must connect to sdi_tx_line_f1 input signal on TX/Du top. |
Pattern Generator Control Module Signals | |||
avmm_clk_in_clk | Input |
1 |
Clock signal to Avalon-MM interface. |
tx_clkout_in_clk | Input |
1 |
Clock signal to Parallel I/O (PIO) IP. This clock must share the same clock as video pattern generator. |
avmm_clk_reset_n | Input |
1 |
Reset signal to Avalon-MM interface. |
pattgen_rst_reset_in0 | Input |
1 |
Input reset signals to a reset synchronizer which synchronizes the reset to the tx_clkout_in_clk clock domain. |
pattgen_rst_reset_in1 | Input |
1 | |
pattgen_rst_reset_out | Input |
1 |
Output reset from the reset synchronizer. This reset synchronizes to the tx_clkout_in_clk clock domain and connects to the video pattern generator’s input reset. |
pattgen_ctrl_pio_out_port | Output |
12 |
Output control signal from PIO to control the video pattern generator. |