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1. Intel® Stratix® 10 Overview
2. Intel® Stratix® 10 JTAG BST Architecture
3. Intel® Stratix® 10 BST Operation Control
4. Intel® Stratix® 10 I/O Voltage for JTAG Operation
5. Performing Intel® Stratix® 10 Boundary-Scan Testing
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry
7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines
8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
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2.4.2. IEEE Std. 1149.6 BST Circuitry for Intel® Stratix® 10 P-Tile Transceiver
Figure 9. HSSI Transmitter BSC for Intel® Stratix® 10 P-Tile Transceiver
Figure 10. HSSI Receiver BSC for Intel® Stratix® 10 P-Tile Transceiver
Figure 11. I_PIN_PERST_N Input Pin BSC for Intel® Stratix® 10 P-Tile Transceiver