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1. Intel® Stratix® 10 Overview
2. Intel® Stratix® 10 JTAG BST Architecture
3. Intel® Stratix® 10 BST Operation Control
4. Intel® Stratix® 10 I/O Voltage for JTAG Operation
5. Performing Intel® Stratix® 10 Boundary-Scan Testing
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry
7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines
8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
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6.1. Enabling BST Circuitry
The IEEE Std. 1149.1 BST circuitry is enabled after the device is configured. If you need to perform the boundary-scan test prior to configuration, you must execute the MISCCTRL instruction upon device power up to enable the BST circuitry.
MISCCTRL Instruction
!Shift 10-bit MISCCTRL instruction (0x013) to Instruction Register
SIR 10 TDI (013);
!Transition to Run-Test-Idle state
STATE IDLE;
!Shift 8-bit data (0x01) to Data Register for BST circuitry enabling
SDR 8 TDI (01);