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1.1. HDMI Intel® FPGA IP v19.7.4
1.2. HDMI Intel® FPGA IP v19.7.3
1.3. HDMI Intel® FPGA IP v19.7.2
1.4. HDMI Intel® FPGA IP v19.7.0
1.5. HDMI Intel® FPGA IP v19.6.1
1.6. HDMI Intel® FPGA IP v19.6.0
1.7. HDMI Intel® FPGA IP v19.5.0
1.8. HDMI Intel® FPGA IP v19.4.0
1.9. HDMI Intel® FPGA IP v19.3.0
1.10. HDMI Intel® FPGA IP v19.1
1.11. HDMI Intel® FPGA IP v18.1 Update 1
1.12. HDMI Intel® FPGA IP v18.1
1.13. HDMI Intel® FPGA IP v18.0
1.14. Intel FPGA HDMI IP Core v17.1
1.15. HDMI IP Core v17.0
1.16. HDMI IP Core v16.1
1.17. HDMI IP Core v16.0
1.18. HDMI IP Core v15.1
1.19. HDMI IP Core v15.0 Update 1
1.20. HDMI IP Core v15.0
1.21. HDMI IP Core v14.1
1.22. HDMI Intel® FPGA IP User Guide Archives
1.23. HDMI Arria® 10 FPGA IP Design Example User Guide Archives
1.24. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives
1.25. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
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Ixiasoft
1.8. HDMI Intel® FPGA IP v19.4.0
Quartus® Prime Version | Description | Impact |
---|---|---|
20.2 | Added support for High-bandwidth Digital Content Protection (HDCP) feature for Stratix® 10 devices. This feature has also been available for Arria® 10 devices since the Quartus® Prime Pro Edition software version 19.3 and later. |
The HDCP feature is not included in the Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html. |
Quartus® Prime Version | Description | Impact |
---|---|---|
20.1 | Added support for deep color implementation for HDMI 2.1 with fixed rate link (FRL) enabled. HDMI 2.1 is available only for Arria® 10 devices. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Enabled a DIP switch (dipsw) for HDMI 2.1 design examples. The switch enables you to toggle between passthrough mode and independent RX and TX mode, which can operate at different link rates. |