High-Definition Multimedia Interface (HDMI) Intel® FPGA IP Release Notes

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Date 4/09/2024
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1. HDMI Intel® FPGA IP Release Notes
1. HDMI Intel® FPGA IP Release Notes x
1.1. HDMI Intel® FPGA IP v19.7.4 1.2. HDMI Intel® FPGA IP v19.7.3 1.3. HDMI Intel® FPGA IP v19.7.2 1.4. HDMI Intel® FPGA IP v19.7.0 1.5. HDMI Intel® FPGA IP v19.6.1 1.6. HDMI Intel® FPGA IP v19.6.0 1.7. HDMI Intel® FPGA IP v19.5.0 1.8. HDMI Intel® FPGA IP v19.4.0 1.9. HDMI Intel® FPGA IP v19.3.0 1.10. HDMI Intel® FPGA IP v19.1 1.11. HDMI Intel® FPGA IP v18.1 Update 1 1.12. HDMI Intel® FPGA IP v18.1 1.13. HDMI Intel® FPGA IP v18.0 1.14. Intel FPGA HDMI IP Core v17.1 1.15. HDMI IP Core v17.0 1.16. HDMI IP Core v16.1 1.17. HDMI IP Core v16.0 1.18. HDMI IP Core v15.1 1.19. HDMI IP Core v15.0 Update 1 1.20. HDMI IP Core v15.0 1.21. HDMI IP Core v14.1 1.22. HDMI Intel® FPGA IP User Guide Archives 1.23. HDMI Arria® 10 FPGA IP Design Example User Guide Archives 1.24. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.25. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
1. HDMI Intel® FPGA IP Release Notes

1.13. HDMI Intel® FPGA IP v18.0

Table 19.  v18.0 May 2018
Description Impact
Renamed Intel FPGA HDMI IP to HDMI Intel® FPGA IP as part of standardizing and rebranding exercise. –
Added preliminary support for Stratix® 10 (H-Tile) devices. The Stratix® 10 devices are only available in the Quartus® Prime Pro Edition software.
Updated the HDMI Intel® FPGA IP to support HDMI Specification 2.0b. These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added support for Xcelium* Parallel simulator.
Added the following files:
  • xcelium_files.tcl
  • xcelium_setup.sh
  • xcelium_sim.sh
Added support for SCDC read request feature in the HDMI RX core.
Added final support for Cyclone® 10 GX devices. The Cyclone® 10 GX devices are only available in the Quartus® Prime Pro Edition software.
Added new design examples for Cyclone® 10 GX devices in version 17.1.1 release. Refer to the HDMI Intel Cyclone 10 GX FPGA IP Design Example User Guide for more information.
Table 20.  Design Files Required for IP Upgrade

The implementation of the IP on hardware requires additional components specific to the device targeted.

These additional components, such as Native PHY, TX PLL, reconfiguration controller, are not included as part of the Quartus® Prime IP Upgrade flow. Upgrading an IP core would require the inclusion of these files generated as part of the IP design example.

Design Example Required Files
Arria® 10
  • quartus\a10_hdmi2_demo.qsf
  • rtl\gxb\gxb_tx_fpll.qsys—regenerate before you compile in the Quartus® Prime software.
  • rtl\hdmi_rx\hdmi_rx_top.v
  • rtl\hdmi_rx\mr_hdmi_rx_core_top.v
  • rtl\reconfig_mgmt\mr_reconfig_mgmt.v
  • rtl\sdc\a10_hdmi2.sdc
  • rtl\a10_hdmi2_demo.v
Cyclone® 10 GX
  • quartus\c10_hdmi2_demo.qsf
  • rtl\sdc\c10_hdmi2.sdc
  • sdc\mr_clock_sync.sdc
  • rtl\sdc\mr_reconfig_mgmt.sdc
  • rtl\sdc\rxtx_link.sdc
  • rtl\c10_hdmi2_demo.v
  • rtl\xcvr_transceiver_arbiter.v
Related Information
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