AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

Download PDF
ID 683197
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface x
1.1. Introduction 1.2. Requirements 1.3. Downloading and Installing the Reference Design 1.4. Walkthrough 1.5. Document Revision History for RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.2. Requirements x
1.2.1. Software Requirements 1.2.2. Hardware Requirements 1.2.3. Features of the RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.4. Walkthrough x
1.4.1. Hardware Setup 1.4.2. Programming the FPGA 1.4.3. Running the Design 1.4.4. System Console User Interface Commands 1.4.5. Register Address Map
1.4.2. Programming the FPGA x
1.4.2.1. Using a Nios® II Command Shell 1.4.2.2. Using the Programmer
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface

1.4.2.2. Using the Programmer

Perform the following steps to program the FPGA using the Programmer:

  1. Launch the Intel® Quartus® Prime software.
  2. Before you begin the FPGA configuration, ensure the following:
    1. The Intel® FPGA Download Cable II driver is installed on the host computer.
    2. The board is powered.
    3. No other application is accessing the JTAG chain.
  3. Connect the Intel® FPGA Download Cable II between your host computer USB port and the USB port on the development board.
  4. On the Tools menu, click Programmer.
  5. Click Auto Detect to display the devices in the JTAG chain and select a device.
  6. Right click and select Change File. Then, select the srio2_s10_avst_6g_de.sof file from the project directory and click Open.
  7. Turn on the Program/Configure option for the srio2_s10_avst_6g_de.sof file.
  8. Click Start to download the srio2_s10_avst_6g_de.sof file to the FPGA. Configuration is complete when the progress bar reaches 100%.
Level Two Title