AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

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ID 683197
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface x
1.1. Introduction 1.2. Requirements 1.3. Downloading and Installing the Reference Design 1.4. Walkthrough 1.5. Document Revision History for RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.2. Requirements x
1.2.1. Software Requirements 1.2.2. Hardware Requirements 1.2.3. Features of the RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.4. Walkthrough x
1.4.1. Hardware Setup 1.4.2. Programming the FPGA 1.4.3. Running the Design 1.4.4. System Console User Interface Commands 1.4.5. Register Address Map
1.4.2. Programming the FPGA x
1.4.2.1. Using a Nios® II Command Shell 1.4.2.2. Using the Programmer
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface

1.3. Downloading and Installing the Reference Design

You can download the reference design from the Design Store. You must have a My Intel® account to gain access to the Design Store.
  1. Download the platform archive file srio2_s10_avst_6g_de.par from the Design Store to your chosen directory.
  2. Open the Intel® Quartus® Prime software, click File > Open Project.
  3. Browse to select the srio2_s10_avst_6g_de.par file.
  4. Click Open.
  5. The Open Design Template window appears. For Project name, enter srio2_s10_avst_6g_de.
    Figure 2. Open Design Template
  6. Click OK.
    After you open the srio2_s10_avst_6g_de.par file in the Intel® Quartus® Prime software, you can see the following directory structure.
    Figure 3. Directory Structure for the Reference Design Example
    Table 1.  Reference Design Files
    File Name Description
    srio2_s10_avst_6g_de.qpf Intel® Quartus® Prime project file containing the list of all the revisions in the project.
    srio2_s10_avst_6g_de.qsf Intel® Quartus® Prime settings file containing the assignments and settings for the project.
    jtag_timing_template.sdc Defines the timing constraints for JTAG.
    srio2_s10_avst_6g_de.sof Pre-generated programming file.
    top_srio.v Top-level design file.
    traffic_gen.v Traffic generator module.
    traffic_chk.v Traffic checker module.
    stats.v Statistics collecting module.
    top_srio.sdc Top-level timing constraints file.
    srio2.stp Pre-populated Signal Tap file.
    ip/srio RapidIO II IP sub folder contains all of the required synthesis files for the core.
    srio.ip RapidIO II IP variation file that contains the parameterization of an IP core in your project.
    components/atx_pll Contains all the necessary synthesis files for the ATX PLL.
    components/xcvr_rst_ctl Contains all the necessary synthesis files for the Transceiver Reset Controller.
    components/client_decode Contains all the necessary synthesis files for the Client Decode Platform Designer based subsystems.
    components/ip Contains all of the Client Decode underlying sub IP block IP variation files. Created during the Client Decode system generation and this file is required to compile the design.
    atx_pll.ip Intel® Stratix® 10 ATX PLL IP variation file.
    xcvr_rst_ctl.ip Intel® Stratix® 10 Transceiver Reset Controller IP variation file.
    client_decode.qsys Platform Designer subsystems contains a JTAG Master and several Avalon® -MM bridges used to decode the JTAG Avalon® -MM address for the different Avalon® -MM slave interface.
    basic.tcl Defines basic register read and write procedures.
    lpbk_ctl.tcl Defines TX to RX PMA buffer serial loopback control.
    main_run.tcl Contains main call to the other .tcl files.
    srio_tasks.tcl Defines the majority of the RapidIO II related functions and procedures for controlling the traffic generator/checker and the statistics collector.
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