AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

Download PDF
ID 683197
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface x
1.1. Introduction 1.2. Requirements 1.3. Downloading and Installing the Reference Design 1.4. Walkthrough 1.5. Document Revision History for RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.2. Requirements x
1.2.1. Software Requirements 1.2.2. Hardware Requirements 1.2.3. Features of the RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.4. Walkthrough x
1.4.1. Hardware Setup 1.4.2. Programming the FPGA 1.4.3. Running the Design 1.4.4. System Console User Interface Commands 1.4.5. Register Address Map
1.4.2. Programming the FPGA x
1.4.2.1. Using a Nios® II Command Shell 1.4.2.2. Using the Programmer
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface

1.1. Introduction

The RapidIO II reference design for the Avalon® Streaming ( Avalon® -ST) pass-through interface demonstrates the use of the Avalon® -ST pass-through interface to implement NWRITE transactions using the RapidIO II IP.

You can use the Avalon® -ST pass-through interface of the RapidIO II IP to implement RapidIO transaction types not available by our logical layer (for example, message passing and data streaming). Additionally, you can use this interface to implement custom functions not specified by the RapidIO protocol but applicable to a specific system.

The Avalon® -ST pass-through interface is an optional interface that is generated when you select the Avalon-ST pass-through interface in the Transport and Maintenance page of the RapidIO II IP parameter editor.

Figure 1. RapidIO II Avalon® -ST Pass-Through Interface Reference Design Block Diagram

The RapidIO II reference design for Avalon® -ST pass-through interface includes a traffic generator. The traffic generator initiates NWRITE RapidIO transactions and drives the RapidIO II IP Avalon® -ST source. The design also includes a traffic checker which sinks the RapidIO transactions and is connected to the RapidIO II IP Avalon® -ST sink.

Related Information
Level Two Title