AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

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ID 683197
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface x
1.1. Introduction 1.2. Requirements 1.3. Downloading and Installing the Reference Design 1.4. Walkthrough 1.5. Document Revision History for RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.2. Requirements x
1.2.1. Software Requirements 1.2.2. Hardware Requirements 1.2.3. Features of the RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.4. Walkthrough x
1.4.1. Hardware Setup 1.4.2. Programming the FPGA 1.4.3. Running the Design 1.4.4. System Console User Interface Commands 1.4.5. Register Address Map
1.4.2. Programming the FPGA x
1.4.2.1. Using a Nios® II Command Shell 1.4.2.2. Using the Programmer
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface

1.2.3. Features of the RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface

The reference design has the following features:
  • 4x Mode
  • 6.250 Gbaud
  • 156.25 MHz Reference Clock
  • Avalon® -ST Pass-Through Interface
Level Two Title