V-Series Transceiver PHY IP Core User Guide

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ID 683171
Date 7/26/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Protocol-Specific and Native Transceiver PHYs 2. Getting Started Overview 3. 10GBASE-R PHY IP Core 4. Backplane Ethernet 10GBASE-KR PHY IP Core 5. 1G/10Gbps Ethernet PHY IP Core 6. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core 7. XAUI PHY IP Core 8. Interlaken PHY IP Core 9. PHY IP Core for PCI Express (PIPE) 10. Custom PHY IP Core 11. Low Latency PHY IP Core 12. Deterministic Latency PHY IP Core 13. Stratix V Transceiver Native PHY IP Core 14. Arria V Transceiver Native PHY IP Core 15. Arria V GZ Transceiver Native PHY IP Core 16. Cyclone V Transceiver Native PHY IP Core Overview 17. Transceiver Reconfiguration Controller IP Core Overview 18. Transceiver PHY Reset Controller IP Core 19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices 20. Analog Parameters Set Using QSF Assignments 21. Migrating from Stratix IV to Stratix V Devices Overview 22. Additional Information for the Transceiver PHY IP Core
1. Introduction to the Protocol-Specific and Native Transceiver PHYs x
1.1. Protocol-Specific Transceiver PHYs 1.2. Native Transceiver PHYs 1.3. Non-Protocol-Specific Transceiver PHYs 1.4. Transceiver PHY Modules 1.5. Transceiver Reconfiguration Controller 1.6. Resetting the Transceiver PHY 1.7. Running a Simulation Testbench 1.8. Unsupported Features
2. Getting Started Overview x
2.1. Installation and Licensing of IP Cores 2.2. Design Flows 2.3. MegaWizard Plug-In Manager Flow
2.3. MegaWizard Plug-In Manager Flow x
2.3.1. Specifying Parameters 2.3.2. Simulate the IP Core
3. 10GBASE-R PHY IP Core x
3.1. 10GBASE-R PHY Release Information 3.2. 10GBASE-R PHY Device Family Support 3.3. 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices 3.4. 10GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices 3.5. 10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices 3.6. Parameterizing the 10GBASE-R PHY 3.7. General Option Parameters 3.8. Analog Parameters for Stratix IV Devices 3.9. 10GBASE-R PHY Interfaces 3.10. 10GBASE-R PHY Data Interfaces 3.11. 10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces 3.12. Optional Reset Control and Status Interface 3.13. 10GBASE-R PHY Clocks for Arria V GT Devices 3.14. 10GBASE-R PHY Clocks for Arria V GZ Devices 3.15. 10GBASE-R PHY Clocks for Stratix IV Devices 3.16. 10GBASE-R PHY Clocks for Stratix V Devices 3.17. 10GBASE-R PHY Register Interface and Register Descriptions 3.18. 10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices 3.19. 10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices 3.20. 1588 Delay Requirements 3.21. 10GBASE-R PHY TimeQuest Timing Constraints 3.22. 10GBASE-R PHY Simulation Files and Example Testbench
4. Backplane Ethernet 10GBASE-KR PHY IP Core x
4.1. 10GBASE-KR PHY Release Information 4.2. Device Family Support 4.3. 10GBASE-KR PHY Performance and Resource Utilization 4.4. Parameterizing the 10GBASE-KR PHY 4.5. 10GBASE-KR PHY IP Core Functional Description 4.6. 10GBASE-KR Dynamic Reconfiguration from 1G to 10GbE 4.7. 10GBASE-KR PHY Arbitration Logic Requirements 4.8. 10GBASE-KR PHY State Machine Logic Requirements 4.9. Forward Error Correction (Clause 74) 4.10. 10BASE-KR PHY Interfaces 4.11. 10GBASE-KR PHY Clock and Reset Interfaces 4.12. Register Interface Signals 4.13. 10GBASE-KR PHY Register Definitions 4.14. PMA Registers 4.15. PCS Registers 4.16. Creating a 10GBASE-KR Design 4.17. Editing a 10GBASE-KR MIF File 4.18. Design Example 4.19. SDC Timing Constraints 4.20. Acronyms
4.4. Parameterizing the 10GBASE-KR PHY x
4.4.1. 10GBASE-KR Link Training Parameters 4.4.2. 10GBASE-KR Auto-Negotiation and Link Training Parameters 4.4.3. 10GBASE-R Parameters 4.4.4. 1GbE Parameters 4.4.5. Speed Detection Parameters 4.4.6. PHY Analog Parameters
4.11. 10GBASE-KR PHY Clock and Reset Interfaces x
4.11.1. 10GBASE-KR PHY Data Interfaces 4.11.2. 10GBASE-KR PHY Control and Status Interfaces 4.11.3. Daisy-Chain Interface Signals 4.11.4. Embedded Processor Interface Signals 4.11.5. Dynamic Reconfiguration Interface Signals
4.11.1. 10GBASE-KR PHY Data Interfaces x
4.11.1.1. 10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data 4.11.1.2. 10GBASE-KR PHY Serial Data Interface 4.11.1.3. MII Interface Signals
5. 1G/10Gbps Ethernet PHY IP Core x
5.1. 1G/10GbE PHY Release Information 5.2. Device Family Support 5.3. 1G/10GbE PHY Performance and Resource Utilization 5.4. Parameterizing the 1G/10GbE PHY 5.5. 1GbE Parameters 5.6. Speed Detection Parameters 5.7. PHY Analog Parameters 5.8. 1G/10GbE PHY Interfaces 5.9. 1G/10GbE PHY Clock and Reset Interfaces 5.10. 1G/10GbE PHY Data Interfaces 5.11. XGMII Mapping to Standard SDR XGMII Data 5.12. MII Interface Signals 5.13. Serial Data Interface 5.14. 1G/10GbE Control and Status Interfaces 5.15. Register Interface Signals 5.16. 1G/10GbE PHY Register Definitions 5.17. PMA Registers 5.18. PCS Registers 5.19. 1G/10GbE GMII PCS Registers 5.20. GIGE PMA Registers 5.21. 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE 5.22. 1G/10GbE PHY Arbitration Logic Requirements 5.23. 1G/10GbE PHY State Machine Logic Requirements 5.24. Editing a 1G/10GbE MIF File 5.25. Creating a 1G/10GbE Design 5.26. Dynamic Reconfiguration Interface Signals 5.27. Design Example 5.28. Simulation Support 5.29. TimeQuest Timing Constraints 5.30. Acronyms
6. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core x
6.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 6.2. Using the IP Core 6.3. Configuration Registers 6.4. Interface Signals
6.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
6.1.1. Features 6.1.2. Release Information 6.1.3. Device Family Support 6.1.4. Resource Utilization
6.2. Using the IP Core x
6.2.1. Parameter Settings 6.2.2. Timing Constraints 6.2.3. Changing the PHY's Speed
6.3. Configuration Registers x
6.3.1. Register Map 6.3.2. Configuration Registers
6.4. Interface Signals x
6.4.1. Clock and Reset Signals 6.4.2. Operating Mode and Speed Signals 6.4.3. GMII Signals 6.4.4. XGMII Signals 6.4.5. Status Signals 6.4.6. Serial Interface Signals 6.4.7. Transceiver Status and Reconfiguration Signals 6.4.8. Avalon® Memory-Mapped Interface Signals
7. XAUI PHY IP Core x
7.1. XAUI PHY Release Information 7.2. XAUI PHY Device Family Support 7.3. XAUI PHY Performance and Resource Utilization for Stratix IV Devices 7.4. XAUI PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices 7.5. Parameterizing the XAUI PHY 7.6. XAUI PHY General Parameters 7.7. XAUI PHY Analog Parameters 7.8. XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices 7.9. Advanced Options Parameters 7.10. XAUI PHY Configurations 7.11. XAUI PHY Ports 7.12. XAUI PHY Data Interfaces 7.13. XAUI PHY Clocks, Reset, and Powerdown Interfaces 7.14. XAUI PHY PMA Channel Controller Interface 7.15. XAUI PHY Optional PMA Control and Status Interface 7.16. XAUI PHY Register Interface and Register Descriptions 7.17. XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX 7.18. XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices 7.19. SDC Timing Constraints 7.20. Simulation Files and Example Testbench
7.12. XAUI PHY Data Interfaces x
7.12.1. SDR XGMII TX Interface 7.12.2. SDR XGMII RX Interface 7.12.3. Transceiver Serial Data Interface
7.18. XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices x
7.18.1. Logical Lane Assignment Restriction 7.18.2. XAUI PHY Dynamic Reconfiguration Interface Signals
8. Interlaken PHY IP Core x
8.1. Interlaken PHY Device Family Support 8.2. Parameterizing the Interlaken PHY 8.3. Interlaken PHY General Parameters 8.4. Interlaken PHY Optional Port Parameters 8.5. Interlaken PHY Analog Parameters 8.6. Interlaken PHY Interfaces 8.7. Interlaken PHY Avalon-ST TX Interface 8.8. Interlaken PHY Avalon-ST RX Interface 8.9. Interlaken PHY TX and RX Serial Interface 8.10. Interlaken PHY PLL Interface 8.11. Interlaken Optional Clocks for Deskew 8.12. Interlaken PHY Register Interface and Register Descriptions 8.13. Why Transceiver Dynamic Reconfiguration 8.14. Dynamic Transceiver Reconfiguration Interface 8.15. Interlaken PHY TimeQuest Timing Constraints 8.16. Interlaken PHY Simulation Files and Example Testbench
9. PHY IP Core for PCI Express (PIPE) x
9.1. PHY for PCIe (PIPE) Device Family Support 9.2. PHY for PCIe (PIPE) Resource Utilization 9.3. Parameterizing the PHY IP Core for PCI Express (PIPE) 9.4. PHY for PCIe (PIPE) General Options Parameters 9.5. PHY for PCIe (PIPE) Interfaces 9.6. PHY for PCIe (PIPE) Input Data from the PHY MAC 9.7. PHY for PCIe (PIPE) Output Data to the PHY MAC 9.8. PHY for PCIe (PIPE) Clocks 9.9. PHY for PCIe (PIPE) Clock SDC Timing Constraints for Gen3 Designs 9.10. PHY for PCIe (PIPE) Optional Status Interface 9.11. PHY for PCIe (PIPE) Serial Data Interface 9.12. PHY for PCIe (PIPE) Register Interface and Register Descriptions 9.13. PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate 9.14. Enabling Dynamic PMA Tuning for PCIe Gen3 9.15. PHY for PCIe (PIPE) Dynamic Reconfiguration 9.16. PHY for PCIe (PIPE) Simulation Files and Example Testbench
9.13. PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate x
9.13.1. Phase 0 9.13.2. Phase 1 9.13.3. Phase 2 (Optional) 9.13.4. Phase 3 (Optional) 9.13.5. Recommendations for Tuning Link Partner’s Transmitter
9.15. PHY for PCIe (PIPE) Dynamic Reconfiguration x
9.15.1. Logical Lane Assignment Restriction
10. Custom PHY IP Core x
10.1. Device Family Support 10.2. Performance and Resource Utilization 10.3. Parameterizing the Custom PHY 10.4. Interfaces
10.3. Parameterizing the Custom PHY x
10.3.1. General Options Parameters 10.3.2. Word Alignment Parameters 10.3.3. Rate Match FIFO Parameters 10.3.4. 8B/10B Encoder and Decoder Parameters 10.3.5. Byte Order Parameters 10.3.6. PLL Reconfiguration Parameters 10.3.7. Analog Parameters 10.3.8. Presets for Ethernet
10.4. Interfaces x
10.4.1. Data Interfaces 10.4.2. Clock Interface 10.4.3. Optional Status Interface 10.4.4. Optional Reset Control and Status Interface 10.4.5. Register Interface and Register Descriptions 10.4.6. Custom PHY IP Core Registers 10.4.7. SDC Timing Constraints 10.4.8. Dynamic Reconfiguration
10.4.6. Custom PHY IP Core Registers x
10.4.6.1. PMA Common Control and Status Registers 10.4.6.2. Reset Control Registers–Automatic Reset Controller 10.4.6.3. Reset Controls –Manual Mode 10.4.6.4. PMA Control and Status Registers 10.4.6.5. Custom PCS
11. Low Latency PHY IP Core x
11.1. Device Family Support 11.2. Performance and Resource Utilization 11.3. Parameterizing the Low Latency PHY 11.4. General Options Parameters 11.5. Additional Options Parameters 11.6. PLL Reconfiguration Parameters 11.7. Low Latency PHY Analog Parameters 11.8. Low Latency PHY Interfaces 11.9. Low Latency PHY Data Interfaces 11.10. Optional Status Interface 11.11. Low Latency PHY Clock Interface 11.12. Optional Reset Control and Status Interface 11.13. Register Interface and Register Descriptions 11.14. Dynamic Reconfiguration 11.15. SDC Timing Constraints 11.16. Simulation Files and Example Testbench
12. Deterministic Latency PHY IP Core x
12.1. Deterministic Latency Auto-Negotiation 12.2. Achieving Deterministic Latency 12.3. Deterministic Latency PHY Delay Estimation Logic 12.4. Deterministic Latency PHY Device Family Support 12.5. Parameterizing the Deterministic Latency PHY 12.6. Interfaces for Deterministic Latency PHY 12.7. Data Interfaces for Deterministic Latency PHY 12.8. Clock Interface for Deterministic Latency PHY 12.9. Optional TX and RX Status Interface for Deterministic Latency PHY 12.10. Optional Reset Control and Status Interfaces for Deterministic Latency PHY 12.11. Register Interface and Descriptions for Deterministic Latency PHY 12.12. Dynamic Reconfiguration for Deterministic Latency PHY 12.13. Channel Placement and Utilization for Deterministic Latency PHY 12.14. SDC Timing Constraints 12.15. Simulation Files and Example Testbench for Deterministic Latency PHY
12.5. Parameterizing the Deterministic Latency PHY x
12.5.1. General Options Parameters for Deterministic Latency PHY 12.5.2. Additional Options Parameters for Deterministic Latency PHY 12.5.3. PLL Reconfiguration Parameters for Deterministic Latency PHY 12.5.4. Deterministic Latency PHY Analog Parameters
13. Stratix V Transceiver Native PHY IP Core x
13.1. Device Family Support for Stratix V Native PHY 13.2. Performance and Resource Utilization for Stratix V Native PHY 13.3. Parameter Presets 13.4. Parameterizing the Stratix V Native PHY 13.5. Interfaces for Stratix V Native PHY 13.6. ×6/×N Bonded Clocking 13.7. xN Non-Bonded Clocking 13.8. SDC Timing Constraints of Stratix V Native PHY 13.9. Dynamic Reconfiguration for Stratix V Native PHY 13.10. Simulation Support 13.11. Slew Rate Settings
13.4. Parameterizing the Stratix V Native PHY x
13.4.1. General Parameters for Stratix V Native PHY 13.4.2. PMA Parameters for Stratix V Native PHY 13.4.3. Standard PCS Parameters for the Native PHY 13.4.4. 10G PCS Parameters for Stratix V Native PHY 10G TX FIFO 10G RX FIFO Interlaken Frame Generator Interlaken Frame Synchronizer Interlaken CRC32 Generator and Checker 10GBASE-R BER Checker 64b/66b Encoder and Decoder Scrambler and Descrambler Parameters Interlaken Disparity Generator and Checker Block Synchronization Gearbox PRBS Verifier
13.4.3. Standard PCS Parameters for the Native PHY x
13.4.3.1. Standard PCS Pattern Generators
13.4.4. 10G PCS Parameters for Stratix V Native PHY x
10G TX FIFO 10G RX FIFO Interlaken Frame Generator Interlaken Frame Synchronizer Interlaken CRC32 Generator and Checker 10GBASE-R BER Checker 64b/66b Encoder and Decoder Scrambler and Descrambler Parameters Interlaken Disparity Generator and Checker Block Synchronization Gearbox PRBS Verifier 13.4.4.1. 10G PCS Pattern Generators
13.5. Interfaces for Stratix V Native PHY x
13.5.1. Common Interface Ports for Stratix V Native PHY 13.5.2. Standard PCS Interface Ports 13.5.3. 10G PCS Interface
14. Arria V Transceiver Native PHY IP Core x
14.1. Device Family Support 14.2. Performance and Resource Utilization 14.3. Parameterizing the Arria V Native PHY 14.4. General Parameters 14.5. PMA Parameters 14.6. Standard PCS Parameters 14.7. Interfaces 14.8. SDC Timing Constraints 14.9. Dynamic Reconfiguration 14.10. Simulation Support 14.11. Slew Rate Settings
14.5. PMA Parameters x
14.5.1. TX PMA Parameters 14.5.2. TX PLL Parameters 14.5.3. RX PMA Parameters
14.6. Standard PCS Parameters x
14.6.1. Phase Compensation FIFO 14.6.2. Byte Ordering Block Parameters 14.6.3. Byte Serializer and Deserializer 14.6.4. 8B/10B 14.6.5. Rate Match FIFO 14.6.6. Word Aligner and BitSlip Parameters 14.6.7. Bit Reversal and Polarity Inversion
14.7. Interfaces x
14.7.1. Common Interface Ports 14.7.2. Standard PCS Interface Ports
15. Arria V GZ Transceiver Native PHY IP Core x
15.1. Device Family Support for Arria V GZ Native PHY 15.2. Performance and Resource Utilization for Arria V GZ Native PHY 15.3. Parameter Presets 15.4. Parameterizing the Arria V GZ Native PHY 15.5. Interfaces for Arria V GZ Native PHY 15.6. SDC Timing Constraints of Arria V GZ Native PHY 15.7. Dynamic Reconfiguration for Arria V GZ Native PHY 15.8. Simulation Support 15.9. Slew Rate Settings
15.4. Parameterizing the Arria V GZ Native PHY x
15.4.1. General Parameters for Arria V GZ Native PHY 15.4.2. PMA Parameters for Arria V GZ Native PHY 15.4.3. Standard PCS Parameters for the Native PHY 15.4.4. 10G PCS Parameters for Arria V GZ Native PHY
15.4.3. Standard PCS Parameters for the Native PHY x
15.4.3.1. Standard PCS Pattern Generators
15.4.4. 10G PCS Parameters for Arria V GZ Native PHY x
15.4.4.1. 10G PCS Pattern Generators
15.5. Interfaces for Arria V GZ Native PHY x
15.5.1. Common Interface Ports for Arria V GZ Native PHY 15.5.2. Standard PCS Interface Ports 15.5.3. 10G PCS Interface
16. Cyclone V Transceiver Native PHY IP Core Overview x
16.1. Cyclone Device Family Support 16.2. Cyclone V Native PHY Performance and Resource Utilization 16.3. Parameterizing the Cyclone V Native PHY 16.4. General Parameters 16.5. PMA Parameters 16.6. Standard PCS Parameters 16.7. Interfaces 16.8. SDC Timing Constraints 16.9. Dynamic Reconfiguration 16.10. Simulation Support 16.11. Slew Rate Settings
16.5. PMA Parameters x
16.5.1. TX PMA Parameters 16.5.2. TX PLL Parameters 16.5.3. RX PMA Parameters
16.6. Standard PCS Parameters x
16.6.1. Phase Compensation FIFO 16.6.2. Byte Ordering Block Parameters 16.6.3. Byte Serializer and Deserializer 16.6.4. 8B/10B 16.6.5. Rate Match FIFO 16.6.6. Word Aligner and BitSlip Parameters 16.6.7. Bit Reversal and Polarity Inversion
16.7. Interfaces x
16.7.1. Common Interface Ports 16.7.2. Cyclone V Standard PCS Interface Ports
17. Transceiver Reconfiguration Controller IP Core Overview x
17.1. Transceiver Reconfiguration Controller System Overview 17.2. Transceiver Reconfiguration Controller Performance and Resource Utilization 17.3. Parameterizing the Transceiver Reconfiguration Controller IP Core 17.4. Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys 17.5. Transceiver Reconfiguration Controller Interfaces 17.6. Transceiver Reconfiguration Controller Memory Map 17.7. Transceiver Reconfiguration Controller Calibration Functions 17.8. Transceiver Reconfiguration Controller PMA Analog Control Registers 17.9. Transceiver Reconfiguration Controller EyeQ Registers 17.10. Transceiver Reconfiguration Controller DFE Registers 17.11. Controlling DFE Using Register-Based Reconfiguration 17.12. Transceiver Reconfiguration Controller AEQ Registers 17.13. Transceiver Reconfiguration Controller ATX PLL Calibration Registers 17.14. Transceiver Reconfiguration Controller PLL Reconfiguration 17.15. Transceiver Reconfiguration Controller PLL Reconfiguration Registers 17.16. Transceiver Reconfiguration Controller DCD Calibration Registers 17.17. Transceiver Reconfiguration Controller Channel and PLL Reconfiguration 17.18. Transceiver Reconfiguration Controller Streamer Module Registers 17.19. MIF Generation 17.20. Creating MIFs for Designs that Include Bonded or GT Channels 17.21. MIF Format 17.22. xcvr_diffmifgen Utility 17.23. Reduced MIF Creation 17.24. Changing Transceiver Settings Using Register-Based Reconfiguration 17.25. Changing Transceiver Settings Using Streamer-Based Reconfiguration 17.26. Pattern Generators for the Stratix V and Arria V GZ Native PHYs 17.27. Understanding Logical Channel Numbering 17.28. Two PHY IP Core Instances Each with Non-Bonded Channels 17.29. Transceiver Reconfiguration Controller to PHY IP Connectivity 17.30. Merging TX PLLs In Multiple Transceiver PHY Instances 17.31. Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs 17.32. Loopback Modes
17.4. Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys x
17.4.1. General Options Parameters
17.5. Transceiver Reconfiguration Controller Interfaces x
17.5.1. MIF Reconfiguration Management Avalon-MM Master Interface 17.5.2. Transceiver Reconfiguration Interface 17.5.3. Reconfiguration Management Interface
17.7. Transceiver Reconfiguration Controller Calibration Functions x
17.7.1. Offset Cancellation 17.7.2. Duty Cycle Calibration 17.7.3. Auxiliary Transmit (ATX) PLL Calibration
17.9. Transceiver Reconfiguration Controller EyeQ Registers x
17.9.1. EyeQ Usage Example
17.11. Controlling DFE Using Register-Based Reconfiguration x
17.11.1. Turning on DFE Continuous Adaptive mode 17.11.2. Turning on Triggered DFE Mode 17.11.3. Setting the First Tap Value Using DFE in Manual Mode
17.17. Transceiver Reconfiguration Controller Channel and PLL Reconfiguration x
17.17.1. Channel Reconfiguration 17.17.2. PLL Reconfiguration
17.18. Transceiver Reconfiguration Controller Streamer Module Registers x
17.18.1. Mode 0 Streaming a MIF for Reconfiguration 17.18.2. Mode 1 Avalon-MM Direct Writes for Reconfiguration
17.24. Changing Transceiver Settings Using Register-Based Reconfiguration x
17.24.1. Register-Based Write 17.24.2. Register-Based Read
17.25. Changing Transceiver Settings Using Streamer-Based Reconfiguration x
17.25.1. Direct Write Reconfiguration 17.25.2. Streamer-Based Reconfiguration
17.26. Pattern Generators for the Stratix V and Arria V GZ Native PHYs x
17.26.1. Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration 17.26.2. Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration 17.26.3. Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration 17.26.4. Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based Reconfiguration
17.27. Understanding Logical Channel Numbering x
17.27.1. Two PHY IP Core Instances Each with Four Bonded Channels 17.27.2. One PHY IP Core Instance with Eight Bonded Channels
18. Transceiver PHY Reset Controller IP Core x
18.1. Device Family Support for Transceiver PHY Reset Controller 18.2. Performance and Resource Utilization for Transceiver PHY Reset Controller 18.3. Parameterizing the Transceiver PHY Reset Controller IP 18.4. Transceiver PHY Reset Controller Parameters 18.5. Transceiver PHY Reset Controller Interfaces 18.6. Timing Constraints for Bonded PCS and PMA Channels
19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices x
19.1. Parameterizing the Transceiver PLL PHY 19.2. Transceiver PLL Parameters 19.3. Transceiver PLL Signals
20. Analog Parameters Set Using QSF Assignments x
20.1. Making QSF Assignments Using the Assignment Editor 20.2. Analog Settings for Arria V Devices 20.3. Analog Settings for Arria V GZ Devices 20.4. Analog Settings for Cyclone V Devices 20.5. Analog Settings for Stratix V Devices
20.2. Analog Settings for Arria V Devices x
20.2.1. Analog Settings for Arria V Devices 20.2.2. Analog Settings Having Global or Computed Values for Arria V Devices
20.2.1. Analog Settings for Arria V Devices x
20.2.1.1. XCVR_IO_PIN_TERMINATION 20.2.1.2. XCVR_REFCLK_PIN_TERMINATION 20.2.1.3. XCVR_TX_SLEW_RATE_CTRL 20.2.1.4. XCVR_VCCR_ VCCT_VOLTAGE
20.2.2. Analog Settings Having Global or Computed Values for Arria V Devices x
20.2.2.1. CDR_BANDWIDTH_PRESET 20.2.2.2. PLL_BANDWIDTH_PRESET 20.2.2.3. XCVR_RX_DC_GAIN 20.2.2.4. XCVR_ANALOG_SETTINGS_PROTOCOL 20.2.2.5. XCVR_RX_COMMON_MODE_VOLTAGE 20.2.2.6. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.2.2.7. XCVR_RX_SD_ENABLE 20.2.2.8. XCVR_RX_SD_OFF 20.2.2.9. XCVR_RX_SD_ON 20.2.2.10. XCVR_RX_SD_THRESHOLD 20.2.2.11. XCVR_TX_COMMON_MODE_VOLTAGE 20.2.2.12. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.2.2.13. XCVR_TX_RX_DET_ENABLE 20.2.2.14. XCVR_TX_RX_DET_MODE 20.2.2.15. XCVR_TX_VOD 20.2.2.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.3. Analog Settings for Arria V GZ Devices x
20.3.1. Analog Settings for Arria V GZ Devices 20.3.2. Analog Settings Having Global or Computed Default Values for Arria V GZ Devices
20.3.1. Analog Settings for Arria V GZ Devices x
20.3.1.1. XCVR_IO_PIN_TERMINATION 20.3.1.2. XCVR_REFCLK_PIN_TERMINATION 20.3.1.3. XCVR_RX_BYPASS_EQ_STAGES_234 20.3.1.4. XCVR_TX_SLEW_RATE_CTRL 20.3.1.5. XCVR_VCCA_VOLTAGE 20.3.1.6. XCVR_VCCR_VCCT_VOLTAGE
20.3.2. Analog Settings Having Global or Computed Default Values for Arria V GZ Devices x
20.3.2.1. CDR_BANDWIDTH_PRESET 20.3.2.2. master_ch_number 20.3.2.3. PLL_BANDWIDTH_PRESET 20.3.2.4. reserved_channel 20.3.2.5. XCVR_ANALOG_SETTINGS_PROTOCOL 20.3.2.6. XCVR_RX_DC_GAIN 20.3.2.7. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.3.2.8. XCVR_RX_COMMON_MODE_VOLTAGE 20.3.2.9. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 20.3.2.10. XCVR_RX_SD_ENABLE 20.3.2.11. XCVR_RX_SD_OFF 20.3.2.12. XCVR_RX_SD_ON 20.3.2.13. XCVR_RX_SD_THRESHOLD 20.3.2.14. XCVR_TX_COMMON_MODE_VOLTAGE 20.3.2.15. XCVR_TX_PRE_EMP_PRE_TAP_USER 20.3.2.16. XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 20.3.2.17. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.3.2.18. XCVR_TX_PRE_EMP_2ND_POST_TAP 20.3.2.19. XCVR_TX_PRE_EMP_INV_2ND_TAP 20.3.2.20. XCVR_TX_PRE_EMP_INV_PRE_TAP 20.3.2.21. XCVR_TX_PRE_EMP_PRE_TAP 20.3.2.22. XCVR_TX_RX_DET_ENABLE 20.3.2.23. XCVR_TX_RX_DET_MODE 20.3.2.24. XCVR_TX_RX_DET_OUTPUT_SEL 20.3.2.25. XCVR_TX_VOD 20.3.2.26. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.4. Analog Settings for Cyclone V Devices x
20.4.1. XCVR_IO_PIN_TERMINATION 20.4.2. XCVR_REFCLK_PIN_TERMINATION 20.4.3. XCVR_TX_SLEW_RATE_CTRL 20.4.4. XCVR_VCCR_ VCCT_VOLTAGE 20.4.5. Analog Settings Having Global or Computed Values for Cyclone V Devices
20.4.5. Analog Settings Having Global or Computed Values for Cyclone V Devices x
20.4.5.1. CDR_BANDWIDTH_PRESET 20.4.5.2. PLL_BANDWIDTH_PRESET 20.4.5.3. XCVR_ANALOG_SETTINGS_PROTOCOL 20.4.5.4. XCVR_RX_DC_GAIN 20.4.5.5. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.4.5.6. XCVR_RX_COMMON_MODE_VOLTAGE 20.4.5.7. XCVR_RX_SD_ENABLE 20.4.5.8. XCVR_RX_SD_OFF 20.4.5.9. XCVR_RX_SD_ON 20.4.5.10. XCVR_RX_SD_THRESHOLD 20.4.5.11. XCVR_TX_COMMON_MODE_VOLTAGE 20.4.5.12. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.4.5.13. XCVR_TX_RX_DET_ENABLE 20.4.5.14. XCVR_TX_RX_DET_MODE 20.4.5.15. XCVR_TX_VOD 20.4.5.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.5. Analog Settings for Stratix V Devices x
20.5.1. Analog PCB Settings for Stratix V Devices 20.5.2. Analog Settings Having Global or Computed Default Values for Stratix V Devices
20.5.1. Analog PCB Settings for Stratix V Devices x
20.5.1.1. XCVR_GT_IO_PIN_TERMINATION 20.5.1.2. XCVR_IO_PIN_TERMINATION 20.5.1.3. XCVR_REFCLK_PIN_TERMINATION 20.5.1.4. XCVR_RX_BYPASS_EQ_STAGES_234 20.5.1.5. XCVR_TX_SLEW_RATE_CTRL 20.5.1.6. XCVR_VCCA_VOLTAGE 20.5.1.7. XCVR_VCCR_VCCT_VOLTAGE
20.5.2. Analog Settings Having Global or Computed Default Values for Stratix V Devices x
20.5.2.1. CDR_BANDWIDTH_PRESET 20.5.2.2. master_ch_number 20.5.2.3. PLL_BANDWIDTH_PRESET 20.5.2.4. reserved_channel 20.5.2.5. XCVR_ANALOG_SETTINGS_PROTOCOL 20.5.2.6. XCVR_GT_RX_DC_GAIN 20.5.2.7. XCVR_RX_DC_GAIN 20.5.2.8. XCVR_RX_LINEAR_EQUALIZER_CONTROL 20.5.2.9. XCVR_GT_RX_COMMON_ MODE_VOLTAGE 20.5.2.10. XCVR_GT_RX_CTLE 20.5.2.11. XCVR_GT_TX_COMMON_ MODE_VOLTAGE 20.5.2.12. XCVR_GT_TX_PRE_EMP_1ST_POST_TAP 20.5.2.13. XCVR_GT_TX_PRE_EMP_ INV_PRE_TAP 20.5.2.14. XCVR_GT_TX_PRE_EMP_ PRE_TAP 20.5.2.15. XCVR_GT_TX_VOD_MAIN_TAP 20.5.2.16. XCVR_RX_COMMON_MODE_VOLTAGE 20.5.2.17. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 20.5.2.18. XCVR_RX_SD_ENABLE 20.5.2.19. XCVR_RX_SD_OFF 20.5.2.20. XCVR_RX_SD_ON 20.5.2.21. XCVR_RX_SD_THRESHOLD 20.5.2.22. XCVR_TX_COMMON_MODE_VOLTAGE 20.5.2.23. XCVR_TX_PRE_EMP_PRE_TAP_USER 20.5.2.24. XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 20.5.2.25. XCVR_TX_PRE_EMP_1ST_POST_TAP 20.5.2.26. XCVR_TX_PRE_EMP_2ND_POST_TAP 20.5.2.27. XCVR_TX_PRE_EMP_INV_2ND_TAP 20.5.2.28. XCVR_TX_PRE_EMP_INV_PRE_TAP 20.5.2.29. XCVR_TX_PRE_EMP_PRE_TAP 20.5.2.30. XCVR_TX_RX_DET_ENABLE 20.5.2.31. XCVR_TX_RX_DET_MODE 20.5.2.32. XCVR_TX_RX_DET_OUTPUT_SEL 20.5.2.33. XCVR_TX_VOD 20.5.2.34. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
21. Migrating from Stratix IV to Stratix V Devices Overview x
21.1. Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers 21.2. Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices 21.3. Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices 21.4. Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices 21.5. Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V Devices 21.6. Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices 21.7. Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices
22. Additional Information for the Transceiver PHY IP Core x
22.1. Revision History for Previous Releases of the Transceiver PHY IP Core 22.2. How to Contact Intel
1. Introduction to the Protocol-Specific and Native Transceiver PHYs
2. Getting Started Overview
3. 10GBASE-R PHY IP Core
4. Backplane Ethernet 10GBASE-KR PHY IP Core
5. 1G/10Gbps Ethernet PHY IP Core
6. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
7. XAUI PHY IP Core
8. Interlaken PHY IP Core
9. PHY IP Core for PCI Express (PIPE)
10. Custom PHY IP Core
11. Low Latency PHY IP Core
12. Deterministic Latency PHY IP Core
13. Stratix V Transceiver Native PHY IP Core
14. Arria V Transceiver Native PHY IP Core
15. Arria V GZ Transceiver Native PHY IP Core
16. Cyclone V Transceiver Native PHY IP Core Overview
17. Transceiver Reconfiguration Controller IP Core Overview
18. Transceiver PHY Reset Controller IP Core
19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices
20. Analog Parameters Set Using QSF Assignments
21. Migrating from Stratix IV to Stratix V Devices Overview
22. Additional Information for the Transceiver PHY IP Core

13.4.4. 10G PCS Parameters for Stratix V Native PHY

This section shows the complete datapath and clocking for the 10G PCS and defines parameters available in the GUI to enable or disable the individual blocks in the 10G PCS.

Figure 67. The 10G PCS datapath
Table 202.  General and Datapath Parameters
Parameter Range Description
10G PCS protocol mode

basic

interlaken

sfis

teng_baser

teng_1588

teng_sdi

Specifies the protocol that you intend to implement with the Native PHY. The protocol mode selected guides the MegaWizard in identifying legal settings for the 10G PCS datapath. Use the following guidelines to select a protocol mode:
  • basic : Select this mode for when none of the other options are appropriate. You should also select this mode to enable diagnostics, such as loopback.
  • interlaken: Select this mode if you intend to implement Interlaken.
  • sfis : Select this mode if you intend to implement the SERDES Framer Interface Level 5 protocol.
  • teng_baser : select this mode if you intend to implement the 10GBASE‑R protocol.

  • teng_1588: select this mode if you intend to implement the 10GBASE‑R protocol with the 1588 precision time stamping feature.

  • teng_sdi : 10G SDI
10G PCS/PMA interface width 32, 40, 64 Specifies the width of the datapath that connects the FPGA fabric to the PMA.
FPGA fabric/10G PCS interface width

32, 40, 50

64, 66, 67

Specifies the FPGA fabric to TX PCS interface width .

The 66-bit FPGA fabric/PCS interface width is achieved using 64-bits from the TX and RX parallel data and the lower 2-bits from the control bus.

The 67-bit FPGA fabric/PCS interface width is achieved using the 64-bits from the TX and RX parallel data and the lower 3-bits from the control bus.

10G TX FIFO

The TX FIFO is the interface between TX data from the FPGA fabric and the PCS. This FIFO is an asynchronous 73-bit wide, 32-deep memory buffer It also provides full, empty, partially full, and empty flags based on programmable thresholds. The following table describes the 10G TX FIFO parameters.

Table 203.  10G TX FIFO Parameters
Parameter Range Description
TX FIFO Mode

Interlaken

phase_comp

register

Specifies one of the following 3 modes:
  • interlaken : The TX FIFO acts as an elastic buffer. The FIFO write clock frequency (coreclk) can exceed that of the effective read clock, tx_clkout. You can control writes to the FIFO with tx_data_valid. By monitoring the FIFO flags, you can avoid the FIFO full and empty conditions. The Interlaken frame generator controls reads.
  • phase_comp : The TX FIFO compensates for the clock phase difference between the coreclkin and tx_clkout which is an internal PCS clock.
  • register : The TX FIFO is bypassed. tx_data and tx_data_valid are registered at the FIFO output. You must control tx_data_valid precisely based on gearbox ratio to avoid gearbox underflow or overflow conditions.
TX FIFO full threshold 0-31 Specifies the full threshold for the 10G PCS TX FIFO. The active high TX FIFO full flag is synchronous to coreclk. The default value is 31.
TX FIFO empty threshold 0-31 Specifies the empty threshold for the 10G PCS TX FIFO. The active high TX FIFO empty flag is synchronous to coreclk. The default value is 0.
TX FIFO partially full threshold 0-31 Specifies the partially full threshold for the 10G PCS TX FIFO. The active high TX FIFO partially full flag is synchronous to coreclk. The default value is 23.
TX FIFO partially empty threshold 0-31 Specifies the partially empty threshold for the 10G PCS TX FIFO. The active high TX FIFO partially empty flag is synchronous to coreclk.
Enable tx_10g_fifo_full port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_fifo_full port. tx_10g_fifo_full is synchronous to coreclk.
Enable tx_10g_fifo_pfull port On/Off When you turn this option On , the 10G PCS includes the active high tx_10g_fifo_pfull port. tx_10g_fifo_pfull is synchronous to coreclk.
Enable tx_10g_fifo_empty port On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_fifo_empty port. tx_10g_fifo_empty is pulse‑stretched. It is asynchronous to coreclk and synchronous to tx_clkout which is the read clock.
Enable tx_10g_fifo_pempty port On/Off When you turn this option On, the 10G PCS includes the tx_10g_fifo_pempty port.
Enable tx_10g_fifo_del port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_fifo_del port. This signal is asserted when a word is deleted from the TX FIFO. This signal is only used for the 10GBASE‑R protocol.
Enable tx_10g_fifo_insert port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the active high tx_10g_fifo_insert port. This signal is asserted when a word is inserted into the TX FIFO. This signal is only used for the 10GBASE‑R protocol.

10G RX FIFO

The RX FIFO is the interface between RX data from the FPGA fabric and the PCS. This FIFO is an asynchronous 73-bit wide, 32-deep memory buffer It also provides full, empty, partially full, and empty flags based on programmable thresholds. The following table describes the 10G RX FIFO parameters.

Table 204.  10G RX FIFO Parameters
Parameter Range Description
RX FIFO Mode

Interlaken

clk_comp

phase_comp

register

Specifies one of the following 3 modes:
  • interlaken : Select this mode for the Interlaken protocol. To implement the deskew process. In this mode the FIFO acts as an elastic buffer. The FIFO write clock can exceed the read clock. Your implementation must control the FIFO write (tx_datavalid) by monitoring the FIFO flags. The read enable is controlled by the Interlaken Frame Generator.
  • clk_comp : This mode compensates for the clock difference between the PLD clock (coreclkin) and rxclkout. After block lock is achieved, idle ordered set insertions and deletions compensate for the clock difference between RX PMA clock and PLD clock up to ± 100 ppm. Use this mode for 10GBASE‑R.
  • phase_comp : This mode compensates for the clock phase difference between the PLD clock (coreclkin) and rxclkout.
  • register : The TX FIFO is bypassed. rx_data and rx_data_valid are registered at the FIFO output.
RX FIFO full threshold 0-31 Specifies the full threshold for the 10G PCS RX FIFO. The default value is 31.
RX FIFO empty threshold 0-31 Specifies the empty threshold for the 10G PCS RX FIFO. The default value is 0.
RX FIFO partially full threshold 0-31 Specifies the partially full threshold for the 10G PCS RX FIFO. The default value is 23.
RX FIFO partially empty threshold 0-31 Specifies the partially empty threshold for the 10G PCS RX FIFO.
Enable RX FIFO alignment word deletion (Interlaken) On/Off When you turn this option On, all alignment words (sync words), including the first sync word, are removed after frame synchronization is achieved. If you enable this option, you must also enable control word deletion.
Enable RX FIFO control word deletion (Interlaken) On/Off When you turn this option On , the rx_control_del parameter enables or disables writing the Interlaken control word to RX FIFO. When disabled, a value of 0 for rx_control_del writes all control words to RX FIFO. When enabled, a value of 1 deletes all control words and only writes the data to the RX FIFO.
Enable rx_10g_fifo_data_valid port On/Off When you turn this option On, the 10G PCS includes the rx_data_valid signal which Indicates when rx_data is valid. This option is available when you select the following parameters:
  • 10G PCS protocol mode is Interlaken
  • 10G PCS protocol mode is Basic and RX FIFO mode is phase_comp
  • 10G PCS protocol mode is Basic and RX FIFO mode is register
Enable rx_10g_fifo_full port On/Off When you turn this option On, the 10G PCS includes the active high rx_10g_fifo_full port. rx_10g_fifo_full is synchronous to rx_clkout.
Enable rx_10g_fifo_pfull port On/Off When you turn this option On, the 10G PCS includes the active high rx_10g_fifo_pfull port. rx_10g_fifo_pfull is synchronous to rx_clkout.
Enable rx_10g_fifo_empty port On/Off When you turn this option On, the 10G PCS includes the active high rx_10g_fifo_empty port.
Enable rx_10g_fifo_pempty port On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_pempty port.
Enable rx_10g_fifo_del port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_del port. This signal is asserted when a word is deleted from the RX FIFO. This signal is only used for the 10GBASE‑R protocol.
Enable rx_10g_fifo_insert port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_insert port. This signal is asserted when a word is inserted into the RX FIFO. This signal is only used for the 10GBASE‑R protocol.
Enable rx_10g_fifo_rd_en port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_rd_en input port. Asserting this signal reads a word from the RX FIFO. This signal is only available for the Interlaken protocol.
Enable rx_10g_fifo_align_val port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_val output port. This signal is asserted when the word alignment pattern is found. This signal is only available for the Interlaken protocol.
enable rx10g_clk33out port On/Off When you turn this option On, the 10G PCS includes a divide by 33 clock output port. You typically need this option when the fabric to PCS interface width is 66.
Enable rx_10g_fifo_align_clr port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_clr input port. When this signal is asserted, the FIFO resets and begins searching for a new alignment pattern. This signal is only available for the Interlaken protocol.
Enable rx_10g_fifo_align_en port (Interlaken) On/Off When you turn this option On, the 10G PCS includes the rx_10g_fifo_align_en input port. This signal is used for FIFO deskew for Interlaken. When asserted, the corresponding channel is enabled for alignment. This signal is only available for the Interlaken protocol.

Interlaken Frame Generator

TX Frame generator generates the metaframe. It encapsulates the payload from MAC with the framing layer control words, including sync, scrambler, skip and diagnostic words. The following table describes the Interlaken frame generator parameters.

Table 205.  Interlaken Frame Generator Parameters
Parameter Range Description
teng_tx_framgen_enable On/Off When you turn this option On, the frame generator block of the 10G PCS is enabled.
teng_tx_framgen_user_length 0-8192 Specifies the metaframe length.
teng_tx_framgen_burst_enable On/Off When you turn this option On, the frame generator burst functionality is enabled.
Enable tx_10g_frame port On/Off When you turn this option On, the 10G PCS includes the tx_10g_frame output port. When asserted, tx_10g_frame indicates the beginning of a new metaframe inside the frame generator.
Enable tx_10g_frame_diag_status port On/Off When you turn this option On, the 10G PCS includes the tx_10g_frame_diag_status 2‑bit input port. This port contains the lane Status Message from the framing layer Diagnostic Word, bits[33:32]. This message is inserted into the next Diagnostic Word generated by the frame generation block. The message must be held static for 5 cycles before and 5 cycles after the tx_frame pulse.
Enable tx_10g_frame_burst_en port On/Off When you turn this option On, the 10G PCS includes the tx_10g_frame_burst_en input port. This port controls frame generator data reads from the TX FIFO. The value of this signal is latched once at the beginning of each Metaframe. It controls whether data is read from the TX FIFO or SKIP Words are inserted for the current Metaframe. It must be held static for 5 cycles before and 5 cycles after the tx_frame pulse. When tx_10g_frame_burst_en is 0, the frame generator does not read data from the TX FIFO for current Metaframe. It insert SKIPs. When tx_10g_frame_burst_en is 1, the frame generator reads data from the TX FIFO for current Metaframe.

Interlaken Frame Synchronizer

The Interlaken frame synchronizer block achieves lock by looking for four synchronization words in consecutive metaframes. After synchronization, the frame synchronizer monitors the scrambler word in the metaframe and deasserts the lock signal after three consecutive mismatches and starts the synchronization process again. Lock status is available to the FPGA fabric. The following table describes the Interlaken frame synchronizer parameters.

Table 206.  Interlaken Frame Synchronizer Parameters
Parameter Range Description
teng_tx_framsync_enable On/Off When you turn this option On, the 10G PCS frame generator is enabled.
Enable rx_10g_frame port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame output port. This signal is asserted to indicate the beginning of a new metaframe inside.
Enable rx_10g_frame_lock_port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_lock output port. This signal is asserted to indicate that the frame synchronization state machine has achieved frame lock.
Enable rx_10g_frame_mfrm_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_mfrm_err output port. This signal is asserted to indicate an metaframe error.
Enable rx_10g_frame_sync_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_sync_err output port. This signal is asserted to indicate synchronization control word errors. This signal remains asserted during the loss of block_lock and does not update until block_lock is recovered.
Enable rx_10g_frame_skip_ins port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_skip_ins output port. This signal is asserted to indicate a SKIP word was received by the frame sync in a non‑SKIP word location within the metaframe.
Enable rx_10g_frame_pyld_ins port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_pyld_ins output port. This signal is asserted to indicate a SKIP word was not received by the frame sync in a SKIP word location within the metaframe.
Enable rx_10g_frame_skip_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_skip_err output port. This signal is asserted to indicate the frame synchronization has received an erroneous word in a Skip control word location within the Metaframe. This signal remains asserted during the loss of block_lock and does update until block_lock is recovered.
Enable rx_10g_frame_diag_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_diag_err output port. This signal is asserted to indicate a diagnostic control word error. This signal remains asserted during the loss of block_lock and does update until block_lock is recovered.
Enable rx_10g_frame_diag_status port On/Off When you turn this option On, the 10G PCS includes the rx_10g_frame_diag_status 2‑bit output port per channel. This port contains the lane Status Message from the framing layer Diagnostic Word, bits[33:32]. This message is inserted into the next Diagnostic Word generated by the frame generation block.

Interlaken CRC32 Generator and Checker

CRC-32 provides a diagnostic tool on a per-lane basis. You can use CRC-32 to trace interface errors back to an individual lane. The CRC-32 calculation covers the whole metaframe including the Diagnostic Word itself. This CRC code value is stored in the CRC32 field of the Diagnostic Word. The following table describes the CRC-32 parameters.

Table 207.  Interlaken CRC32 Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX CRC32 Generator On/Off When you turn this option On, the TX 10G PCS datapath includes the CRC32 function.
Enable Interlaken RX CRC32 Generator On/Off When you turn this option On, the RX 10G PCS datapath includes the CRC32 function.
Enable rx_10g_crc32_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_crc32_err port. This signal is asserted to indicate that the CRC checker has found an error in the current metaframe.

10GBASE-R BER Checker

The BER monitor block conforms to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. After block lock is achieved, the BER monitor starts to count the number of invalid synchronization headers within a 125-us period. If more than 16 invalid synchronization headers are observed in a 125-us period, the BER monitor provides the status signal to the FPGA fabric, indicating a high bit error. The following table describes the 10GBASE-R BER checker parameters.

Table 208.  10GBASE-R BER Checker Parameters
Parameter Range Description
Enable rx_10g_highber port (10GBASE‑R) On/Off When you turn this option On, the TX 10G PCS datapath includes the rx_10g_highber output port. This signal is asserted to indicate a BER of >10 4 . A count of 16 errors in 125‑ m s period indicates a BER > 10 4 . This signal is only available for the 10GBASE‑R protocol.
Enable rx_10g_highber_clr_cnt port (10GBASE‑R) On/Off When you turn this option On, the TX 10G PCS datapath includes the rx_10g_highber_clr_cnt input port. When asserted, the BER counter resets to 0. This signal is only available for the 10GBASE‑R protocol.
Enable rx_10g_clr_errblk_count port (10GBASE‑R) On/Off When you turn this option On, the 10G PCS includes the rx_10g_clr_errblk_count input port. When asserted, error block counter that counts the number of RX errors resets to 0. This signal is only available for the 10GBASE‑R protocol.

64b/66b Encoder and Decoder

The 64b/66b encoder and decoder conform to the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49. The 64b/66b encoder sub-block receives data from the TX FIFO and encodes the 64-bit data and 8-bit control characters to the 66-bit data block required by the 10GBASE-R protocol. The transmit state machine in the 64b/66b encoder sub-block checks the validity of the 64-bit data from the MAC layer and ensures proper block sequencing.

The 64b/66b decoder sub-block converts the received data from the descrambler into 64-bit data and 8-bit control characters. The receiver state machine sub-block monitors the status signal from the BER monitor. The following table describes the 64/66 encoder and decoder parameters.

Table 209.  64b/66b Encoder and Decoder Parameters
Parameter Range Description
Enable TX sync header error insertion On/Off When you turn this option On, the 10G PCS records. This parameter is valid for the Interlaken and 10GBASE‑R protocols.
Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the TX 64b/66b encoder.
Enable TX 64b/66b encoder On/Off When you turn this option On, the 10G PCS includes the RX 64b/66b decoder.

Scrambler and Descrambler Parameters

TX scrambler randomizes data to create transitions to create DC-balance and facilitate CDR circuits based on the x58 + x39 +1 polynomial. The scrambler operates in the following two modes:

  • Synchronous—The Interlaken protocol requires synchronous mode.
  • Asynchronous (also called self-synchronized)—The 10GBASE-R protocol requires this mode as specified in IEEE 802.3-2008 Clause-49.

The descrambler block descrambles received data to regenerate unscrambled data using the x58+x39+1 polynomial. The following table describes the scrambler and descrambler parameters.

Table 210.  Scrambler and Descrambler Parameters
Parameter Range Description
Enable TX scrambler On/Off When you turn this option On, the TX 10G PCS datapath includes the scrambler function. This option is available for the Interlaken and 10GBASE‑R protocols.
TX scrambler seed User‑specified 15-bit value You must provide a different seed for each lane. This parameter is only required for the Interlaken protocol.
Enable RX scrambler On/Off When you turn this option On, the RX 10G PCS datapath includes the scrambler function. This option is available for the Interlaken and 10GBASE‑R protocols.
Enable rx_10g_descram_err port On/Off When you turn this option On, the 10G PCS includes the rx_10g_descram_err port.

Interlaken Disparity Generator and Checker

The Disparity Generator monitors the data transmitted to ensure that the running disparity remains within a ±96-bit bound. It adds the 67th bit to indicate whether or not the data is inverted. The Disparity Checker monitors the status of the 67th bit of the incoming word to determine whether or not to invert bits[63:0] of the received word. The following table describes Interlaken disparity generator and checker parameters.

Table 211.  Interlaken Disparity Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX disparity generator On/Off When you turn this option On, the 10G PCS includes the disparity generator. This option is available for the Interlaken protocol.
Enable Interlaken RX disparity generator On/Off When you turn this option On, the 10G PCS includes the disparity checker. This option is available for the Interlaken protocol.

Block Synchronization

The block synchronizer determines the block boundary of a 66-bit word for the 10GBASE-R protocol or a 67-bit word for the Interlaken protocol. The incoming data stream is slipped one bit at a time until a valid synchronization header (bits 65 and 66) is detected in the received data stream. After the predefined number of synchronization headers is detected, the block synchronizer asserts rx_10g_blk_lock to other receiver PCS blocks down the receiver datapath and to the FPGA fabric. The block synchronizer is designed in accordance with both the Interlaken protocol specification and the 10GBASE-R protocol specification as described in IEEE 802.3-2008 Clause-49.

Table 212.  Bit Reversal and Polarity Inversion Parameters
Parameter Range Description
Enable RX block synchronizer On/Off When you turn this option On, the 10G PCS includes the RX block synchronizer. This option is available for the Interlaken and 10GBASE‑R protocols.
Enable rx_10g_blk_lock port On/Off When you turn this option On, the 10G PCS includes the rx_10G_blk_lock output port. This signal is asserted to indicate the receiver has achieved block synchronization. This option is available for the Interlaken, 10GBASE‑R, and other protocols that user the PCS lock state machine to achieve and monitor block synchronization.
Enable rx_10g_blk_sh_err port On/Off When you turn this option On, the 10G PCS includes the rx_10G_blk_sh_err output port. This signal is asserted to indicate that an invalid sync header has been received. This signal is active after block lock is achieved. This option is available for the Interlaken, 10GBASE‑R, and other protocols that user the PCS lock state machine to achieve and monitor block synchronization.

Gearbox

The gearbox adapts the PMA data width to a wider PCS data width when the PCS is not two or four times the PMA width.

Table 213.  Gearbox Parameters
Parameter Range Description
Enable TX data polarity inversion On/Off When you turn this option On, the gearbox inverts the polarity of TX data allowing you to correct incorrect placement and routing on the PCB.
Enable TX data bitslip On/Off When you turn this option On, the TX gearbox operates in bitslip mode.
Enable RX data polarity inversion On/Off When you turn this option On, the gearbox inverts the polarity of RX data allowing you to correct incorrect placement and routing on the PCB.
Enable RX data bitslip On/Off When you turn this option On, the 10G PCS RX block synchronizer operates in bitslip mode.
Enable tx_10g_bitslip port On/Off When you turn this option On, the 10G PCS includes the tx_10g_bitslip input port. The data slips 1 bit for every positive edge of the tx_10g_bitslip input. The maximum shift is < pcswidth> -1 bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.
Enable rx_10g_bitslip port On/Off When you turn this option On, the 10G PCS includes the rx_10g_bitslip input port. The data slips 1 bit for every positive edge of the rx_10g_bitslip input. he maximum shift is < pcswidth> -1 bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.

PRBS Verifier

You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks support the following patterns:

  • Pseudo-random binary sequence (PRBS)
  • Pseudo-random pattern
  • Square wave
Table 214.  PRBS Parameters
Parameter Range Description
Enable rx_10g_prbs ports On/Off When you turn this option On, the PCS includes the rx_10g_prbs_done , rx_10g_prbs_err and rx_10g_prbs_err_clrsignals to provide status on PRBS operation.

Section Content
10G PCS Pattern Generators

Related Information
Level Two Title