AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.4.1.2. Transmitter Transport Layer

To verify the data integrity of the data stream through the transmitter (TX) JESD204C Intel® FPGA IP and transport layer, the DAC JESD core is configured to check the PRBS test pattern that is transmitted from the test pattern generator of the FPGA. PRBS pattern checker is used to check the data integrity of DAC transport layer.

This figure shows the conceptual test setup for data integrity checking.
Figure 6. Data Integrity Check Using PRBS Pattern Checker
The Signal Tap logic analyzer monitors the operation of the TX transport layer.
Table 8.  TX Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TXTL.1 Check the transport layer mapping of the data channel using PRBS test pattern.
The following signals in <ip_variant_name>_base.v are tapped:
  • j204c_tx_avst_valid
  • j204c_tx_avst_ready
  • j204c_tx_avst_data [(M*S*WIDTH_MULP*N)-1:0]

The txframe_clk is used as the sampling clock for the Signal Tap.

Check the following in the DAC:
  • PRBS test status
  • The j204c_tx_avst_valid and j204c_tx_avst_ready signals are asserted.
  • The PRBS test status in DAC register 0x2064 and 0x2065 does not show an error.
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